View UPD6132MC-XXX-5A4-E2_1662190.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

m pd6133 series remote control transmission sample programs document no. u11726ej1v1an00 (1st edition) date published january 1998 n cp(k) 1997 application note printed in japan
[memo]
the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.
nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j97. 8
introduction readers these application notes are intended for engineers who understand the functions of m pd6133 series infrared remote control transmission microcontrollers and who design application programs using these microcontrollers. purpose the purpose of these application notes is to use application program examples to explain the functions of nec m pd6133 series microcontrollers. organization these application notes can be broadly divided into the following sections. general description ? fundamentals of infrared remote control ? overview of remote control transmission program 48-key program ? hardware configuration ? transmission waveform ? timing charts ? output code ? software configuration ? program description ? cautions on program revisions ? program list 80-key program ? hardware configuration ? transmission waveform ? timing charts ? output code ? software configuration ? program description ? cautions on program revisions ? cautions on use of this program ? program list
legend data representation weight : high-order digits are indicated at left and low-order digits at right. note : explanation of (note) in the text caution : item deserving extra attention remark : supplementary explanation to the text number representation : binary number is xxxxb decimal number is xxxx hexadecimal number is xxxxh related documents the following documentation should be referred to when using this manual. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. document name document number japanese version english version m pd6133, 6134 data sheet u10454j u10454e m pd6604 data sheet u11281j u11281e m pd63, 64 data sheet u11371j u11371e sm6133 version 1.0, u11128j u11128e users manual as6133 assembler u10115j u10115e users manual caution the programs in this document are intended as examples only and are not intended for production design purposes.
C i C contents part 1 general ................................................................................................................... 1 chapter 1 fundamentals of infrared remote control .................................................... 3 chapter 2 overview of remote control transmission program .................................. 5 2.1 general flow chart .......................................................................................................... 5 2.2 overview of processing .................................................................................................. 5 2.2.1 initialization processing ..................................................................................................... 5 2.2.2 stop mode ........................................................................................................................... 5 2.2.3 key input processing .......................................................................................................... 6 2.2.4 transmission processing ................................................................................................... 6 part 2 48-key program ................................................................................................... 7 chapter 1 hardware configuration .......................................................................................... 9 1.1 application circuit example .......................................................................................... 9 1.2 key matrix ....................................................................................................................... 10 chapter 2 transmission waveform ........................................................................................... 11 2.1 nec-r format ................................................................................................................. 11 chapter 3 timing charts ....................................................................................................... ......... 13 3.1 timing charts for key input to rem output ............................................................. 13 3.1.1 timing when a key is pressed and held ........................................................................ 13 3.1.2 timing during key off status ......................................................................................... 14 3.2 timing charts of key operations ............................................................................... 17 3.2.1 output patterns prior to key confirmation .................................................................... 17 3.2.2 operation of combination key ......................................................................................... 23 3.2.3 key transfer operation ...................................................................................................... 25 chapter 4 output codes ........................................................................................................ ........ 27 chapter 5 software configuration ......................................................................................... 29 5.1 general flow chart ........................................................................................................ 29 5.2 program memory (rom) configuration ..................................................................... 30 5.3 data memory (ram) configuration ............................................................................. 32 5.4 flag maps ........................................................................................................................ 37 chapter 6 program description ................................................................................................ 3 9 6.1 initial settings ................................................................................................................. 39 6.1.1 description of processing ................................................................................................ 39 6.1.2 detailed flow chart ............................................................................................................. 43 6.2 key input processing .................................................................................................... 45
C ii C 6.2.1 description of processing ................................................................................................ 45 6.2.2 detailed flow chart ............................................................................................................. 52 6.3 transmission processing ............................................................................................. 65 6.3.1 description of processing ................................................................................................ 66 6.3.2 detailed flow chart ............................................................................................................. 71 chapter 7 cautions on program revisions ........................................................................... 83 chapter 8 program list ........................................................................................................ ......... 85 part 3 80-key program ............................................................................................... 101 chapter 1 hardware configuration ...................................................................................... 103 1.1 application circuit example ...................................................................................... 103 1.2 key matrix ..................................................................................................................... 104 chapter 2 transmission waveform ......................................................................................... 105 2.1 nec-r format ............................................................................................................... 105 chapter 3 timing charts ....................................................................................................... ....... 107 3.1 timing charts for key input to rem output ........................................................... 107 3.1.1 timing when a key is pressed and held ...................................................................... 107 3.1.2 timing during key off status ....................................................................................... 108 3.2 timing charts of key operations ............................................................................. 111 3.2.1 output patterns prior to key confirmation .................................................................. 111 3.2.2 operation of combination key ....................................................................................... 118 3.2.3 key transfer operation .................................................................................................... 120 chapter 4 output codes ........................................................................................................ ...... 121 chapter 5 software configuration ....................................................................................... 123 5.1 general flow chart ...................................................................................................... 123 5.2 program memory (rom) configuration ................................................................... 124 5.3 data memory (ram) configuration ........................................................................... 126 5.4 flag maps ...................................................................................................................... 132 chapter 6 program description .............................................................................................. 133 6.1 initial settings ............................................................................................................... 133 6.1.1 description of processing .............................................................................................. 133 6.1.2 detailed flow chart ........................................................................................................... 137 6.2 key input processing .................................................................................................. 139 6.2.1 description of processing .............................................................................................. 139 6.2.2 detailed flow chart ........................................................................................................... 146 6.3 transmission processing ........................................................................................... 158 6.3.1 description of processing .............................................................................................. 159 6.3.2 detailed flow chart ........................................................................................................... 164
C iii C chapter 7 cautions on program revisions ......................................................................... 175 chapter 8 cautions on use of this program ...................................................................... 177 chapter 9 program list ........................................................................................................ ....... 179
C iv C list of figures (1/2) figure no. title page part 1 general 1-1 configuration of ir remote control unit ............................................................................................. 3 1-2 example of nec-format transmit waveform ....................................................................................... 4 part 2 48-key program 1-1 application circuit example .................................................................................................................. 9 1-2 key matrix ............................................................................................................................... ............. 10 2-1 nec-r format ............................................................................................................................... ...... 11 3-1 timing chart when key is pressed and held .................................................................................... 14 3-2 timing chart for key off status ....................................................................................................... 15 3-3 output patterns prior to key confirmation ........................................................................................ 18 3-4 timing chart of key combination operation ..................................................................................... 23 3-5 operation timing of key transfer operation ..................................................................................... 25 5-1 general flow chart ............................................................................................................................. 29 5-2 rom map ............................................................................................................................... ............. 30 5-3 data table map ............................................................................................................................... .... 31 6-1 chattering of key input signal ........................................................................................................... 45 6-2 key on judgment when chattering occurs ...................................................................................... 46 6-3 48-key key matrix ............................................................................................................................... 47 6-4 key matrix ............................................................................................................................... ............. 48 6-5 key data (key position) ..................................................................................................................... 48 6-6 bit configuration of key data when input is via k i0 to k i3 ................................................................ 49 6-7 bit configuration of key data when input is via s 0 and s 1 ............................................................... 50 6-8 configuration of data pointer ............................................................................................................. 50 6-9 configuration of timer counter .......................................................................................................... 65 6-10 time management of timer counter ................................................................................................. 65 6-11 method for dividing frame space transmission times .................................................................... 69 6-12 key off check during bit data transmission .................................................................................. 70 part 3 80-key program 1-1 application circuit example .............................................................................................................. 103 1-2 key matrix ............................................................................................................................... ........... 104 2-1 nec-r format ............................................................................................................................... .... 105
C v C list of figures (2/2) figure no. title page 3-1 timing chart when key is pressed and held .................................................................................. 108 3-2 timing chart for key off status ..................................................................................................... 109 3-3 output patterns prior to key confirmation ...................................................................................... 112 3-4 timing chart of key combination operation ................................................................................... 118 3-5 operation timing of key transfer operation ................................................................................... 120 5-1 general flow chart ........................................................................................................................... 123 5-2 rom map ............................................................................................................................... ........... 124 5-3 data table map ............................................................................................................................... .. 125 6-1 chattering of key input signal ......................................................................................................... 139 6-2 key on judgment when chattering occurs .................................................................................... 140 6-3 80-key key matrix ............................................................................................................................. 14 1 6-4 key matrix ............................................................................................................................... ........... 142 6-5 key data (key position) ................................................................................................................... 142 6-6 bit configuration of key data when input is via k i0 to k i3 .............................................................. 143 6-7 bit configuration of key data when input is via s 1 ......................................................................... 144 6-8 configuration of data pointer ........................................................................................................... 144 6-9 configuration of timer counter ........................................................................................................ 158 6-10 time management of timer counter ............................................................................................... 158 6-11 method for dividing frame space transmission times .................................................................. 162 6-12 key off check during bit data transmission ................................................................................ 163
C vi C list of tables table no. title page part 2 48-key program 1-1 pin functions ............................................................................................................................... ........ 10 4-1 output codes ............................................................................................................................... ....... 27 5-1 ram map ............................................................................................................................... .............. 32 5-2 map of ram used for key input processing ..................................................................................... 33 5-3 ram map used for transmission processing ................................................................................... 34 5-4 description of ram usage ................................................................................................................. 35 5-5 flag map ............................................................................................................................... ............... 37 6-1 control register 0 (p3) ....................................................................................................................... 40 6-2 time clock and carrier frequency settings ...................................................................................... 40 6-3 control register 1 (p4) ....................................................................................................................... 41 6-4 cancellation conditions for halt instruction .................................................................................... 42 6-5 description of data 1 transmit counter (r9) .................................................................................... 66 6-6 frame space times corresponding to data 1 occurrences ......................................................... 69 part 3 80-key program 1-1 pin functions ............................................................................................................................... ...... 104 4-1 output codes ............................................................................................................................... ..... 121 5-1 ram map ............................................................................................................................... ............ 126 5-2 map of ram used for key input processing ................................................................................... 127 5-3 ram map used for transmission processing ................................................................................. 128 5-4 description of ram usage ............................................................................................................... 129 5-5 flag map ............................................................................................................................... ............. 132 6-1 control register 0 (p3) ..................................................................................................................... 134 6-2 time clock and carrier frequency settings .................................................................................... 134 6-3 control register 1 (p4) ..................................................................................................................... 135 6-4 cancellation conditions for halt instruction .................................................................................. 136 6-5 description of data 1 transmit counter (r9) .................................................................................. 159 6-6 frame space times corresponding to the number of data 1 occurrences ............................... 162
pa rt 1 general
[memo] 2
chapter 1 fundamentals of infrared remote control infrared remote control transmitters (hereafter referred to as ir remote control units or remote control units) interrupt an infrared ray to produce transmission of binary (0 and 1) data whereby various electronic control devices can be operated under remote control. the ir remote control units use of an infrared led (ir-led) as the transmitter diode makes for a smaller remote control transmitter that can be manufactured at less cost. a typical infrared remote control device configuration is shown below. figure 1-1. configuration of ir remote control unit to ensure an effective distance of 7 to 10 meters for remote control transmissions, the current supplied to the ir- led is generally in the range of 300 to 500 ma. however, since this amount of current would shorten the battery life, modulation is used to produce a pulse current wherein the average current is reduced to one tenth or less of the peak current. the infrared rays that are output from the ir-led are re-converted to electrical signals by a photo diode in the receiver. since the received signal is very weak, it is amplified via a receive amplifier before being detected and demodulated into 0 and 1 signals. key source key return key matrix remote control transmitter ic remote control transmitter ic carrier (38 khz) detector (waveform shaper) ir-led av equipment, etc. transmit data ir- led photo diode remote control receiver amp (38 khz) infrared ray (wavelength: 940 nm) output 0 v 3
4 chapter 1 fundamentals of infrared remote control an nec-format transmit waveform is shown below as an example of transmit data from an infrared remote control unit. the ir-led is on (lit) during high-level periods and off (not lit) during low-level periods. figure 1-2. example of nec-format transmit waveform (1) rem output waveform (2) bit data format (3) carrier waveform (4) bit patterns in codes 8.5 s 26.5 s f x = 455 khz carrier frequency: 38 khz dut y factor: 1/3 0.56 ms 0.56 ms data "0" data "1" 1.125 ms 2.25 ms m m c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 0 ' c 0 or c o c 1 ' c 1 or c 1 c 2 ' c 2 or c 2 c 3 ' c 3 or c 3 c 4 ' c 4 or c 4 c 5 ' c 5 or c 5 c 6 ' c 6 or c 6 c 7 ' c 7 or c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 = = = = = = = = data code data code custom code custom code leader code leader code rem output 8 bits custom code custom code' data code data code 8 bits 8 bits 8 bits stop bit frame space 9.00 ms 4.50 ms 27.00 ms 0.56 ms 30.94 to 48.94 ms 18.00 to 36.00 ms
chapter 2 overview of remote control transmission program 2.1 general flow chart 2.2 overview of processing 2.2.1 initialization processing since most remote control units use batteries as their power source, it should be assumed that ram and port contents may undergo sudden changes due to power supply voltage fluctuations during the ir-leds infrared ray emissions. consequently, a program has been implemented to execute ram and port initialization processing when each remote control signal is transmitted. initialization processing includes the following settings. ? port settings, carrier frequency/duty factor, carrier setting ? carrier frequency and timer/clock division settings ? i/o mode settings and pull-down resistor settings for each port 2.2.2 stop mode when in stop mode, program execution is stopped along with system clock oscillation to enable low current consumption. in the remote control program, setting stop mode as a condition for canceling key input enables current consumption to be reduced as long as no key is pressed (while in standby mode). initialization processing key input processing transmission processing remote control transmission stop mode (key input canceled) press another key? no yes 5
6 chapter 2 overview of remote control transmission program 2.2.3 key input processing key input processing includes the following. ? key scanning to determine if any key has been pressed ? ensured reliability in key operations (elimination of chattering) ? generation of key data corresponding to each pressed key, which is stored in ram. 2.2.4 transmission processing transmission processing includes the following. ? transmit data corresponding to the key data generated by key input processing is transmitted according to the specific manufacturers remote control transmission format. ? after the first transmission is completed, the unit detects whether or not the key is still being pressed. ? if it is determined that the key is still being pressed, key input processing checks whether or not the pressed key has changed. ? if it is determined that the key has been released, initialization processing is executed, after which the unit enters stop mode to reduce power consumption until a key is pressed.
pa rt 2 48-key program
[memo] 8
chapter 1 hardware configuration 1.1 application circuit example figure 1-1 shows an application circuit example. figure 1-1. application circuit example note the program is set for on-chip pull-down resistors. the k i , k i/o , s 0 , and s 1 /led pins are used to configure a 48-key key matrix. the transmission code is output via the rem pin with a carrier signal. table 1-1 lists the various pin functions. k i/o6 k i/o7 s 0 note s 1 /led note rem v dd x out x in gnd reset k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 note k i2 note k i1 note k i0 note pd6133 key matrix ( 8 6 = 48 ke y s ) + + m 9
10 chapter 1 hardware configuration table 1-1. pin functions pin name i/o function k i/o0 to k i/o7 output key source (active high) k i0 to k i3 input key return (active high) s 0 input s 1 /led input rem output infrared remote control signal (with carrier) 1.2 key matrix figure 1-2 illustrates the key matrix. the kn symbol (in which n = 1 to 48) indicates each keys position. figure 1-2. key matrix k29 k25 k21 k17 k13 k9 k5 k1 k i/o7 k i/o6 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k30 k26 k22 k18 k14 k10 k6 k2 k31 k27 k23 k19 k15 k11 k7 k3 k32 k28 k24 k20 k16 k12 k8 k4 k47 k45 k43 k41 k39 k37 k35 k33 k48 k46 k44 k42 k40 k38 k36 k34 k i3 k i2 k i1 k i0 s 1 s 0
11 chapter 2 transmission waveform the transmission waveform that is output from the rem pin uses the nec-r (nec continuous) format. for description of the output data code, see chapter 4 output codes. 2.1 nec-r format figure 2-1 illustrates the nec-r format. figure 2-1. nec-r format ? transmission waveform ? transmission waveform for first frame ? transmission waveform for second and subsequent frames ...same as transmission waveform for first frame ? bit data format ? carrier waveform 1 frame (108.00 ms) 1 frame (108.00 ms) transmission (two frames) for one key press when key is pressed and held 8.5 s 26.5 s f x = 455 khz carrier frequency: 38 khz dut y factor: 1/3 0.56 ms 0.56 ms data "0" data "1" 1.125 ms 2.25 ms m m leader code 8 bits custom code custom code' data code data code 8 bits 8 bits 8 bits stop bit frame space 9.00 ms 4.50 ms 27.00 ms 0.56 ms 30.94 to 48.94 ms 18.00 to 36.00 ms
12 [memo]
chapter 3 timing charts 3.1 timing charts for key input to rem output on chattering elimination processing checks for key input every 9.00 ms and if it detects on status three consecutive times, it determines that the key is on. on chattering elimination processing also checks for key status changes (between on and off or when the key is pressed and held). the off chattering elimination processing is described below. key off status is checked during low-level output of the bit data. during transmission of one frame (108 ms), key input is checked ten times with reference to the timing (34 times) of the low-level output from the rem pin. (1) if key off status is detected all ten times ... key off status is determined. (2) if key on status is detected during at least one of the ten times ... when key on status is detected, the check counter is cleared and key input is checked another ten times. (3) if (1) and (2) above do not determine key off status ... key press and hold status (key on status) is determined. even if key off status is determined during transmission of the first frame, initialization processing does not begin until after the second or a subsequent frame is transmitted. 3.1.1 timing when a key is pressed and held figure 3-1 shows a timing chart for when a key is pressed and held. for details of on chattering elimination, see 6.2.1 (1) chattering elimination processing. 13
14 chapter 3 timing charts figure 3-1. timing chart when key is pressed and held key input : actual key operation (manually pressing or releasing a key) software key : software-based key operation (key input judgment by program) rem output : transmission waveform output via rem pin on chattering : this refers to on chattering elimination processing. key input is checked three times at 9.00- ms intervals. off chattering : this refers to off chattering elimination processing. key input is checked throughout the (34- bit) bit space that includes the leader code and stop bit. frame space (1): this frame space is used to maintain a one-frame time of 108.00 ms to modify the transmission time for custom codes. frame space (2): when it is determined that the current frame is the first frame or that a key off status is in effect, frame space (2) is transmitted (during 27.00 ms) without any on chattering elimination processing. 3.1.2 timing during key off status figure 3-2 shows timing charts for when a key is released during a frame transmission. key input rem output on chattering off chattering 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms 27.50 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms frame space (1) frame space (2) off chattering frame space (1) on chattering software key
15 chapter 3 timing charts figure 3-2. timing chart for key off status (1/3) (1) when key is released during transmission of the first frame (key off status has been determined ten times consecutively during transmission of the first frame) ... key off status is confirmed during transmission of second frame (2) when key is released during transmission of the first frame (key off status has not been determined ten times consecutively during transmission of the first frame) ... key off status is confirmed during transmission of second frame key input : actual key operation (manually pressing or releasing a key) software key : software-based key operation (key input judgment by program) rem output : transmission waveform output via rem pin on chattering : this refers to on chattering elimination processing. key input is checked three times at 9.00- ms intervals. off chattering : this refers to off chattering elimination processing. key input is checked throughout the (34- bit) bit space that includes the leader code and stop bit. frame space (1): this frame space is used to maintain a one-frame time of 108.00 ms to modify the transmission time for custom codes. frame space (2): when it is determined that the current frame is the first frame or that a key off status is in effect, frame space (2) is transmitted (during 27.00 ms) without any on chattering elimination processing. rem output key input key off status on chattering 27.50 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms off chattering frame space (1) frame space (2) frame space (1) frame space (2) off chattering key on status key off status key off confirmation software key rem output key input on chattering 27.50 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms off chattering frame space (1) frame space (2) off chattering frame space (1) frame space (2) key on status key off status key off status key off status key off confirmation software key
16 chapter 3 timing charts figure 3-2. timing chart for key off status (2/3) (3) when key is released during transmission of the second frame (key off status has been determined ten times consecutively during transmission of the second frame) ... key off status is confirmed during transmission of second frame (4) when key is released during transmission of the second frame (key off status has not been determined ten times consecutively during transmission of the second frame) ... key off status is confirmed by the key?s on chattering key input : actual key operation (manually pressing or releasing a key) software key : software-based key operation (key input judgment by program) rem output : transmission waveform output via rem pin on chattering : this refers to on chattering elimination processing. key input is checked three times at 9.00- ms intervals. off chattering : this refers to off chattering elimination processing. key input is checked throughout the (34- bit) bit space that includes the leader code and stop bit. frame space (1): this frame space is used to maintain a one-frame time of 108.00 ms to modify the transmission time for custom codes. frame space (2): when it is determined that the current frame is the first frame or that a key off status is in effect, frame space (2) is transmitted (during 27.00 ms) without any on chattering elimination processing. software key key input rem output key off status key off status key on status key off status on chattering off chattering frame space (1) frame space (2) off chattering frame space (1) 0.94 to 18.94 ms 27.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms 27.50 ms 53.06 to 71.06 ms frame space (2) key off confirmation key input software key rem output key off status key on status key off status on chattering off chattering frame space (1) frame space (2) off chattering frame space (1) 0.94 to 18.94 ms 27.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms 27.50 ms 53.06 to 71.06 ms on chattering key off confirmation
17 chapter 3 timing charts figure 3-2. timing chart for key off status (3/3) (5) when key is released during transmission of the first frame and is pressed again later ... key off cannot be confirmed since a key on status is detected during the second frame key input : actual key operation (manually pressing or releasing a key) software key : software-based key operation (key input judgment by program) rem output : transmission waveform output via rem pin on chattering : this refers to on chattering elimination processing. key input is checked three times at 9.00- ms intervals. off chattering : this refers to off chattering elimination processing. key input is checked throughout the (34- bit) bit space that includes the leader code and stop bit. frame space (1): this frame space is used to maintain a one-frame time of 108.00 ms to modify the transmission time for custom codes. frame space (2): when it is determined that the current frame is the first frame or that a key off status is in effect, frame space (2) is transmitted (during 27.00 ms) without any on chattering elimination processing. 3.2 timing charts of key operations 3.2.1 output patterns prior to key confirmation prior to key confirmation, on chattering elimination processing (9.00 ms 3 times = 27.00 ms) is performed and a key is confirmed when it has the same status all 3 times. key input confirmation is determined after at least 100 m s (at least 6 instructions when operating at 455 khz) has elapsed after the key source output pin goes to high level. figure 3-3 shows the detailed output patterns prior to key confirmation. software key key input rem output key off status on chattering off chattering 53.06 to 71.06 ms 27.50 ms 0.94 to 18.94 ms 27.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms frame space (1) frame space (2) off chattering frame space (1) on chattering key on status
18 chapter 3 timing charts figure 3-3. output patterns prior to key confirmation (1/5) (1) when k4 is pressed a: when a key on status has been determined, the key return is checked and the key data is calculated. execution time ranges from approximately 1.34 ms to 1.95 ms. b: key input is checked. execution time is approximately 0.41 ms. c : this is the total output time for key scanning. this time varies according to the value of a. execution time ranges from approximately 4.23 ms to 4.84 ms. b a c 9.0 ms about 0.5 ms k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 s 0 s 1 stop cancel
19 chapter 3 timing charts figure 3-3. output patterns prior to key confirmation (2/5) (2) when k43 is pressed a: when a key on status has been determined, the key return is checked and the key data is calculated. execution time ranges from approximately 1.34 ms to 1.95 ms. b: key input is checked. execution time is approximately 0.41 ms. c : this is the total output time for key scanning. this time varies according to the value of a. execution time ranges from approximately 4.23 ms to 4.84 ms. b a c 9.0 ms about 0.5 ms k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 s 0 s 1 stop cancel
20 chapter 3 timing charts figure 3-3. output patterns prior to key confirmation (3/5) (3) when k29 is pressed along with valid combination key k32 (k29 + k32) a: when a key on status has been determined, the key return is checked and the key data is calculated. execution time ranges from approximately 1.34 ms to 1.95 ms. b: key input is checked. execution time is approximately 0.41 ms. c: this is the total output time for key scanning. this time varies according to the value of a. execution time ranges from approximately 4.23 ms to 4.84 ms. b a c 9.0 ms k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 s 0 s 1
21 chapter 3 timing charts figure 3-3. output patterns prior to key confirmation (4/5) (4) when k9 and k12 are pressed but are invalid in identical key sources a: when a key on status has been determined, the key return is checked and the key data is calculated. execution time ranges from approximately 1.34 ms to 1.95 ms. b: key input is checked. execution time is approximately 0.41 ms. about 0.5 ms k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 s 0 s 1 ba about 0.3 ms stop cancel stop cancel stop cancel stop cancel
22 chapter 3 timing charts figure 3-3. output patterns prior to key confirmation (5/5) (5) when k10 and k16 are pressed but are invalid in identical key sources a: when a key on status has been determined, the key return is checked and the key data is calculated. execution time ranges from approximately 1.34 ms to 1.95 ms. b: key input is checked. execution time is approximately 0.41 ms. about 0.5 ms k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 s 0 s 1 ba stop cancel stop cancel a stop cancel about 0.3 ms
23 chapter 3 timing charts 3.2.2 operation of combination key k29 is the combination key. there are three valid key combination pairs: k29 + k30, k29 + k31, and k29 + k32. for any pattern, a key combination is valid only when k29 is pressed first. in other words, if another key is pressed before or at the same time as k29, the key combination is not valid. figure 3-4 shows examples of key operations when a key combination is entered. figure 3-4. timing chart of key combination operation (1/2) (1) if another valid key (k30 to k32) is pressed during transmission of the first frame of the k29 code, after the second frame of the k29 code is transmitted, the key combination becomes valid and the combinations code is transmitted. (2) if another valid key (from k30 to k32) is pressed during transmission of the third frame of the k29 code, after the k29 code and the third frame are transmitted, the key combination becomes valid and the combinations code is transmitted. rem output k29 key k30 key stop status k29 on chattering transmission of first frame of the k29 code leader code k29 code transmission k29 + k30 code transmission stop cancel data code data code data code k29 off chattering transmission during remaining frame time k29 + k30 on chattering 27.50 ms 108.00 ms 9.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms 27.50 ms rem output k29 key k30 key stop status k29 on chattering transmission of first and second frames of the k29 code 216.00 ms leader code k29 code transmission k29 + k30 code transmission stop cancel data code data code data code data code k29 off chattering transmission during remaining frame time k29 + k30 on chattering 9.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms
24 chapter 3 timing charts figure 3-4. timing chart of key combination operation (2/2) (3) if k29 is pressed after another valid key (k30 to k32) has been confirmed, a key check produces a key error and no code is transmitted (the key combination is not valid). (4) if another valid key (k30 to k32) is pressed before k29 has been confirmed, a key check produces a key error and no code is transmitted (the key combination is not valid). rem output k29 key k30 key stop status 27.50 ms 108.00 ms data code data code 9.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms k29 on chattering transmission of first frame of the k30 code leader code k30 off chattering transmission during remaining frame time transmission during remaining frame time key error status k30 code transmission stop cancel rem output k29 key k30 key 27.00 ms 27.00 ms 27.00 ms 27.00 ms 27.00 ms 27.50 ms on chattering on chattering on chattering on chattering on chattering on chattering stop status stop cancel key error status ?l
25 chapter 3 timing charts 3.2.3 key transfer operation a key transfer operation can be performed when a valid combination key has been pressed. the key transfer operation is an operation that occurs when a second key is pressed before a previously pressed key is released. the operation for the second key is performed when the previous key is released. figure 3-5 shows the operation timing of a key transfer operation. figure 3-5. operation timing of key transfer operation (1) when a key transfer operation is performed to transfer to key b during transmission of the code for key a, a key check is performed after all of the code has been transmitted. a key error occurs if it is during a key combination period. when key a is released, key b becomes valid and its code is transmitted. (2) if the transfer to key b occurs before key a is confirmed, a key error occurs during the key check. a key error also occurs if it is during a key combination period. after key a is released, a key check is performed. key b was released before it could be checked, so the check result is no key. key a 27.50 ms stop status stop cancel no key key a valid keys a and b valid key b valid no key key a on chattering key b on chattering key a code transmission key a off chattering + remaining frame time key b code transmission stop status frame time key b off chattering key error 117.00 ms 72.00 ms 27.00 ms 117.0 ms 53.06 to 71.06 ms 0.94 to 18.94 ms key b - 27.50 ms stop status stop cancel no key key error no key on chattering stop status 27.00 ms 27.00 ms 27.00 ms 27.00 ms 27.00 ms 27.00 ms 27.00 ms 27.00 ms key a key b
[memo] 26
27 chapter 4 output codes table 4-1 lists the output codes. for output using the nec format, nec provides each customer with a custom code to avoid the risk of interfering with output from another remote control unit that outputs using the nec format. this program is set to output 0ah as the custom code and f5h as the custom code. contact your nec sales representative for information on obtaining a custom code. table 4-1. output codes key no. custom custom data key no. custom custom data key no. custom custom data code code code code code code k1 0ah f5h 00h k17 0ah f5h 50h k33 0ah f5h a0h k2 0ah f5h 01h k18 0ah f5h 51h k34 0ah f5h a1h k3 0ah f5h 02h k19 0ah f5h 52h k35 0ah f5h a2h k4 0ah f5h 03h k20 0ah f5h 53h k36 0ah f5h a3h k5 0ah f5h 04h k21 0ah f5h 54h k37 0ah f5h a4h k6 0ah f5h 05h k22 0ah f5h 55h k38 0ah f5h a5h k7 0ah f5h 06h k23 0ah f5h 56h k39 0ah f5h a6h k8 0ah f5h 07h k24 0ah f5h 57h k40 0ah f5h a7h k9 0ah f5h 08h k25 0ah f5h 58h k41 0ah f5h a8h k10 0ah f5h 09h k26 0ah f5h 59h k42 0ah f5h a9h k11 0ah f5h 0ah k27 0ah f5h 5ah k43 0ah f5h aah k12 0ah f5h 0bh k28 0ah f5h 5bh k44 0ah f5h abh k13 0ah f5h 0ch k29 0ah f5h 5ch k45 0ah f5h ach k14 0ah f5h 0dh k30 0ah f5h 5dh k46 0ah f5h adh k15 0ah f5h 0eh k31 0ah f5h 5eh k47 0ah f5h aeh k16 0ah f5h 0fh k32 0ah f5h 5fh k48 0ah f5h afh key no. custom code custom code data k29 + k30 0ah f5h 90h k29 + k31 0ah f5h 91h k29 + k32 0ah f5h 92h
28 [memo]
chapter 5 software configuration 5.1 general flow chart figure 5-1 shows a general flow chart of this program. figure 5-1. general flow chart chattering elimination processing completed 3 times? initialize control register initialize ram and ports set transmit data (access table data) initialize ram used for transmission processing initialize ram used for key input processing key input? valid key? end key scanning? transfer of one frame completed? key off? stop mode (key input cancel) start key scan output generate key data transmit leader code transmit custom code and custom code' transmit data code and data code transmit stop bit transmit frame space yes yes yes yes yes yes no no no no no no chattering time setting (9 ms) halt mode (timer cancel) initialization processing transmission processing key input processing 29
30 chapter 5 software configuration 5.2 program memory (rom) configuration the m pd6133s program memory (rom) consists of 512 steps 10 bits. figure 5-2 shows a rom map for this program and figure 5-3 shows a table data map. figure 5-2. rom map empty space frame space output subroutine data table (see figure 5-3 ) transmit processing empty space key input processing initialization h 0 0 0 h h 3 2 1 1 0 0 h h 4 3 f f 0 0 h h a 9 9 9 1 1 h h d c 9 9 1 1 h h 0 f e d 1 1 h h c b e e 1 1 h f f 1 address program memory
31 chapter 5 software configuration figure 5-3. data table map time data frame space time data key data (k33 to k48) key data (k17 to k32) key data (k1 to k16) key data key combinations: k29+k30, k29+k31 k29+k32 address program memory h f d 1 h h 8 7 d c 1 1 h h 0 f d c 1 1 h h 0 f c b 1 1 h h 0 f b a 1 1 h h 0 f a 9 1 1 h d 9 1
32 chapter 5 software configuration 5.3 data memory (ram) configuration the data memory (ram) consists of 32 4 bits static ram, which is used to store processing data. some instructions enable ram contents to be manipulated in 8 bits units. r0 can function as a data pointer for rom addresses. rom contents can be accessed once a rom address is set to this data pointer. this is called a table lookup for rom data. when reset, the value of r0 becomes 00h. rf can also be used as an address stack register. when reset, the values of r1 to rf are undefined. tables 5-1 to 5-3 show ram maps for the entire program (key input processing and transmission processing), for key input processing alone, and for transmission processing alone. table 5-4 describes ram usage. table 5-1. ram map h (1) l (0) r0 work area 1 chattering counter data pointer h data pointer l r1 confirmation key data h confirmation key data l r2 for immediate setting (0eh) for immediate setting (1h) r3 k29 on flag continue flag r4 key data h key data l custom code h custom code l r5 custom code h custom code l r6 key on flag key scan counter data code h data code l r7 for immediate setting (0fh) key off check counter r8 key scan data h key scan data l for immediate setting (0fh) for immediate setting (0h) data 1 data 0 r9 compare key, data h compare key, data l data 1 transmit counter h data 1 transmit counter l ra work area 2 key return check counter transmit bit counter rb for immediate setting (0ch) for immediate setting (3h) rc not used not used rd not used not used re not used not used rf address stack register
33 chapter 5 software configuration table 5-2. map of ram used for key input processing h (1) l (0) r0 work area 1 chattering counter data pointer h data pointer l r1 confirmation key data h confirmation key data l r2 for immediate setting (0eh) for immediate setting (1h) r3 k29 on flag continue flag r4 key data h key data l custom code h custom code l r5 custom code h custom code l r6 key on flag key scan counter data code h data code l r7 r8 key scan data h key scan data l for immediate setting (0fh) for immediate setting (0h) r9 compare key, data h compare key, data l ra key return check counter rb for immediate setting (0ch) for immediate setting (3h) rc not used not used rd not used not used re not used not used rf address stack register : used for transmission processing
34 chapter 5 software configuration table 5-3. ram map used for transmission processing h (1) l (0) r0 data pointer h data pointer l work area 1 r1 r2 r3 continue flag r4 custom code h custom code l r5 custom code h custom code l r6 data code h data code l r7 for immediate setting (0fh) key off check counter r8 data 1 data 0 r9 data 1 transmit counter h data 1 transmit counter l ra work area 2 transmit bit counter rb rc not used not used rd not used not used re not used not used rf address stack register : used for key input processing
35 chapter 5 software configuration table 5-4. description of ram usage (1/2) name ram description data pointer r0 this pointer is used for indicating rom addresses. it is used when performing a table lookup for rom data. chattering counter r00 this counter is used to count the number of times chattering occurs during key input processing. 0ch is set to this counter as the initial value for a count of three. 0fh indicates completion of three times. work area 1 r10 this is a work area that is used to temporarily store data. confirmation key data r1 this is used to store confirmation key data after on chattering elimination processing has been completed. if other confirmation key data has already been stored, it is compared with the key data (r4) when chattering elimination processing is completed. if the two sets of data match, the previous data is retained. if they do not match, the new key data (r4) is stored. for immediate setting (1h) r02 this is used to clear the high-order three bits or to set 1h. for immediate setting (0eh) r12 this is used to clear the lowest three bits or to set 0eh. continue flag r03 during transmission processing, this flag is used to determine whether it is the first frame or a second or subsequent frame that is currently being transmitted. value description 0fh second or subsequent frame is being transmitted 0h first frame is being transmitted 0fh: set, 0h: clear k29 on flag r13 this flag is used to determine whether or not the k29 key (combination key) has been pressed. value description 0fh k29 key has been pressed 0h key other than k29 key has been pressed 0fh: set, 0h: clear key data r4 this is used to store the previous key data during on chattering. this data is compared with the compare key data (r9). if they match, the previous data is retained. if they do not match, the new compare key data (r9) is stored. custom code r4 this is used to store the custom code. custom code r5 this is used to store the custom code. data code r6 this is used to store the data code. key scan counter r06 this counter is used to count the number of key scans. since a count of eight is required, 8h (8 times) is set as the counters initial value. key on flag r16 this flag is used to determine whether or not a key has been pressed. value description 0fh key has been pressed 0h key has been released 0fh: set, 0h: clear
36 chapter 5 software configuration table 5-4. description of ram usage (2/2) name ram description key off check counter r07 this counter is used to count the number of times key off status occurs during bit data transmission. although a count of ten is required, 5h is set as the initial value. when the value becomes 0fh (meaning ten continuous times of key off status), key off status is confirmed. if key off status is not determined at this time, the counter value is initialized. for immediate setting (0fh) r17 this is used to set various flags. key scan data r8 this is used to store output data for key scanning. data 0 r08 this is used to store the row addresses of time data (table data) for data1 r18 transmitting a bit data value of 0 or 1. data 0: bit data 0 data 1: bit data 1 for immediate setting (0h) r08 this is used to set various flags. for immediate setting (0fh) r18 this is used for flag setting and data inversion. the setting is 0fh. compare key data r9 this is used to store key data during on chattering. data 1 transmit counter r9 this counter is used to count the number of times bit data 1 is transmit- ted. key return check counter r0a this counter is used to calculate the key data based on the key return data. since a count of four is required for k i input and a count of two is required for input of s 0 or s 1 , a initial value of 0ch (for four times) or 0eh (for two times) is set. transmit bit counter r0a during bit transmission processing, this checks whether the required number of transmit bits are in the bit data stored in work area 2 (r1a). the counter counts from one to four times. setting description 0fh 1-bit transmission (for transmitting leader code and stop bit) 0eh 2-bit transmission (not used) 0dh 3-bit transmission (not used) 0ch 4-bit transmission (for transmitting custom code, custom code, data code, and data code) work area 2 r1a this is used to store output data for bit transmissions. for immediate setting (3h) r0b this is used for data judgments and for setting 3h. for immediate setting (0ch) r1b this is used for data judgments and for setting 0ch.
37 chapter 5 software configuration 5.4 flag maps table 5-5 shows flag operations during various types of processing. table 5-5. flag map (1) continue flag (r03) processing r03 initialization processing clear (0h) key input processing when the key data used for on chattering elimination clear (0h) processing differs from the confirmation key data from the previous on chattering elimination processing. transmission processing during frame space transmission of all frames judgment during frame space transmission of only one frame set (0fh) judgment: a judgment is made during this processing. (2) k29 on flag (r13) processing r13 initialization processing clear (0h) key input processing when key is on and flag has been set judgment when chattering has been completed 3 times and the set (0fh) confirmation key data is k29 when chattering has been completed 3 times and the clear (0h) confirmation key data is not k29, nor is there a valid key combination transmission processing C judgment: a judgment is made during this processing. : not used (3) key on flag (r16) processing r16 initialization processing C key input processing during ram initialization clear (0h) start of key return check judgment after key data calculation judgment during key return check or when there is key input set (0fh) after completion of key scanning (8 times) judgment transmission processing judgment: a judgment is made during this processing. : not used, : used by other application
[memo] 38
chapter 6 program description 6.1 initial settings microcontrollers used in infrared remote control transmitters generally use batteries as their power source. however, the lighting of infrared leds requires a large current consumption. the abrupt change in the power supply voltage when infrared leds are being lit can cause sudden changes in the contents of ram, ports, etc., which must be taken into consideration. to prevent operation faults that may occur as a result of sudden changes in the contents of ram, ports, etc., the program can be designed to reset initial settings after each transmission. 6.1.1 description of processing (1) port settings and control register initialization (a) k i/o port (p0) this is an 8-bit i/o port that is used for key scan output. this ports initial setting is ffh. all of the ports bits (k i/o1 to k i/o7 ) are set for high level output. (b) control register 0 (p3) tables 6-1 and 6-2 list the contents of control register 0. the initial setting is 13h. the initial settings are shown in shaded areas in tables 6-1 and 6-2. 39
40 chapter 6 program description table 6-1. control register 0 (p3) bit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 name C C dp (data pointer) tctl cary mod 1 mod 0 dp 9 dp 8 setting 0 fixed as 0 fixed as 0 0 0 1/1 on see table 6-2 . 1 1 1 1/2 off after reset 00000011 b 0 and b 1 ....... specify the rem outputs carrier frequency and duty factor. b 2 ................... indicates presence/absence of carrier for frequency specified by b 0 and b 1 . 0 = on (with carrier), 1 = off (no carrier, high level) b 3 ................... changes the carrier frequency and the timer clock division ratio. 0 = 1/1 (carrier frequency: values set to b 0 and b 1 , timer clock: f x /8) 1 = 1/2 (carrier frequency: one half of values set to b 0 and b 1 , timer clock: f x /16) table 6-2. time clock and carrier frequency settings b 3 b 2 b 1 b 0 timer clock carrier frequency (duty factor) 0000f x /8 f x (duty 1/2) 01 f x /8 (duty 1/2) 10 f x /12 (duty 1/2) 11 f x /12 (duty 1/3) 1 no carrier (high level) 1000f x /16 f x /2 (duty 1/2) 01 f x /16 (duty 1/2) 10 f x /24 (duty 1/2) 11 f x /24 (duty 1/3) 1 no carrier (high level) b 4 and b 5 ....... specify the high-order two bits (dp 8 and dp 9 ) of the rom data pointer. remarks 1. : dont care 2. : initial setting (13h) 3. f x : system clock frequency
41 chapter 6 program description (c) control register 1 (p4) table 6-3 lists the contents of control register 1. the initial setting is 33h, which is shown in the shaded areas of the table. table 6-3. control register 1 (p4) bit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 name C C k i s 0 /s 1 Cs 1 /led k i/o s 0 pull-down pull-down mode mode mode setting 0 fixed as 0 fixed as 0 off off fixed as 0 s 1 in off 1 on on led out in after reset 00100110 b 0 ................... specifies the s 0 ports input mode. 0 = off mode (high impedance), 1 = in (input mode). b 1 ................... specifies the k i/o ports i/o mode. 0 = in (input mode), 1 = out (output mode). b 2 ................... specifies the s 1 /led ports i/o mode. 0 = s 1 (input mode), 1 = led (output mode) b 4 ................... specifies presence/absence of pull-down resistor when s 0 /s 1 port is in input mode. 0 = off (no pull-down), 1 = on (pull-down). b 5 ................... specifies presence/absence of pull-down resistor when k 1 port is in input mode. 0 = off (no pull- down), 1 = on (pull-down). remarks 1. all pull-down resistors are automatically switched off during output mode and off mode. 2. : initial setting (33h) (2) initialize ram the following ram contents are cleared to 0. ? confirmation key data (r1) ? continue flag (r03) ? k29 on flag (r13)
42 chapter 6 program description (3) set stop mode table 6-4 lists the cancellation conditions for the halt instruction. the initial setting is 8h. when initialized, the (stop mode) cancellation conditions are set as shown in the shaded areas of the table. table 6-4. cancellation conditions for halt instruction halt instruction operand value mode precondition for settings cancellation condition b 3 b 2 b 1 b 0 setting 0000 stop high-level output from all k i/o pins high-level input via at least one k i pin 0 1 1 stop high-level output from all k i/o pins high-level input via at least one k i pin 1 1 0 stop note 1 high-level output from k i/o0 pin high-level input via at least one k i pin 1 any combination of stop [the following conditions in addition to the above conditions] b 2 , b 1 , and b 0 above C high-level input via at least one pin between s 0 and s 1 note 2 0/1 1 0 1 halt C when timers down counter reaches 0 notes 1. when halt #x110b is set, use the k i/o0 pin and the k i pin to configure a key matrix so that an internal reset is executed whenever a runaway (control loss) condition occurs. 2. s 0 and/or s 1 (at least one of these pins that are used to cancel standby mode) must be set to input mode (an internal reset will not be executed if both are set to output mode). cautions 1. an internal reset is executed if the halt instruction is executed using operand values other than those specified above or when the precondition for halt instruction execution has not been met. 2. if stop mode is set when the timers down counter has not yet reached 0 (i.e., when the timer is operating), all 10 bits of the enable flags for the timers down counter and the timer output are cleared to zero and stop mode is set. 3. specify a nop instruction as the first instruction following cancellation of stop mode. remark : initial setting (8h) (4) after cancellation of stop mode, execute an nop instruction, then initialize the timer. the timers initial setting is 1ch (= 0.5 ms).
43 chapter 6 program description 6.1.2 detailed flow chart high-level output from all k i/o pins main main processing initialize ports initialize control registers p 13 ? 1h clear status flag set timer counter to 0.5 ms initialize ram nop instruction key48 to ke y input processin g stop mode (cancel key input) (c) (a) (b) (d) (e) (g) (h) (f)
44 chapter 6 program description ******** initialization processing ******** time05m equ 01ch ;0.5ms damytime equ 512-1 ;9.00ms ;########## p u b l i c ########## public main ; ;########## e x t e r n ########## ; ;########## s t a r t ########## ;*********************************************** ; control register initialize ;*********************************************** main: out p0,#0ffh (a) sets all key scan outputs (k i/o ) to high level out p4,#033h (b) initializes ports s 0 , s 1 : input mode, k i/o : output mode out p3,#013h (c) initializes control registers 0 and 1 (p3 and p4) with carrier, frequency: f x /12, duty factor: 1/3 tctl: 1/1, k i : with pull-down resistor s 0 , s 1 : with pull-down resistor data pointer: dp 8 , dp 9 = 01h (msb of table lookup address) mov t,#damytime (d) clears status flags stts #0101b ;*********************************************** ; ram initialize routine ;*********************************************** (e) initializes ram mov r1,#000h confirmation key data (r1): 00h mov r3,#000h k29 on flag (r 13 ), continue flag (r 03 ): 00h halt #008h (f) stop mode: canceled by high-level input via k i , s 0 , and s 1 nop (g) nop instruction mov t,#time05m (h) initializes timer value ; 1ch = 0.5 ms end .....................
45 chapter 6 program description 6.2 key input processing 6.2.1 description of processing key input processing includes chattering elimination processing, key scan processing, custom code generation processing, and key data generation processing. (1) chattering elimination processing when switching to key on or key off status, an unstable condition called chattering (on chattering or off chattering) exists until the key signal is stabilized as a high level or low level signal (see figure 6-1). since key input during this unstable condition is also unstable, the program must provide a means of eliminating chattering. figure 6-1. chattering of key input signal figure 6-2 illustrates an example of chattering elimination processing (key on judgment example). at point <1>, key on status is detected when stop mode is canceled, and key input is checked during a set time period (from <1> to <4>: 9.00 ms 3). in part (a) of the figure, key on status is detected at all check points, so the key signal is judged to be at high level at the software keys <4>. the wait period (a + b + c) after key on status is detected at point <1> and before the software judges the signals high level status is called the chattering elimination period. in part (a), the chattering elimination period is a + b + c since the key input status is always on when checked. in part (b), the chattering elimination period is d + e + f + g + h. key on on chattering key confirmation off chattering key off
46 chapter 6 program description figure 6-2. key on judgment when chattering occurs (a) (b) software key key input abc < 1 > < 2 > < 3 > < 4 > software key key input def gh < 1 > < 2 > < 1 > < 2 > < 3 > < 4 >
47 chapter 6 program description (2) key scan processing key scan processing is described in sections (a) and (b) below. (a) key matrix figure 6-3 shows an example of a 48-key key matrix. in this example, k i/o0 to k i/o7 are output ports that output key scan signals. these signals are captured (as key return signals) via input ports comprised of k i0 to k i3 , s 0 and s 1 . since the program connects these key return signal input ports (k i0 to k i3 , s 0 and s 1 ) to an internal pull- down resistor, low-level signals are input when no keys are being pressed. figure 6-3. 48-key key matrix note the program is set for internal pull-down resistor. (b) key scan to judge which of the keys in the 48-key key matrix is being pressed, the stts instruction is used to check for high-level signal input via k i0 to k i3 , s 0 , and s 1 . k i/o6 k i/o7 s 0 note s 1 /led note k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 note k i2 note k i1 note k i0 note pd6133 key matrix 8 6 = 48 ke y s m
48 chapter 6 program description next, the key scan signals output ports (k i/o0 to k i/o7 ) are set to high level one at a time starting from k i/o0 to determine which output among k i/o0 to k i/o7 corresponds to the detected input. during the key scan processing part of the program, the key scan counter (key source position) and key return check counter (key return position) are used to detect the key data (key position). figure 6-5 shows the correspondence between key data and the values of these two counters. for description of the key datas bit configuration in data memory, see (4) (a) bit configuration of key data. when performing a key scan, factors such as stray capacitance in the keyboard and key source delay due to line impedance must be taken into consideration. therefore, this program waits for about 100 m s (six steps when at 455 khz) following high-level output before capturing the key input. figure 6-4. key matrix figure 6-5. key data (key position) k29 k25 k21 k17 k13 k9 k5 k1 k i/o7 k i/o6 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k30 k26 k22 k18 k14 k10 k6 k2 k31 k27 k23 k19 k15 k11 k7 k3 k32 k28 k24 k20 k16 k12 k8 k4 k47 k45 k43 k41 k39 k37 k35 k33 k48 k46 k44 k42 k40 k38 k36 k34 k i3 k i2 k i1 k i0 s 1 s 0 k29 k25 k21 k17 k13 k9 k5 k1 f e d c b a 9 8 k30 k26 k22 k18 k14 k10 k6 k2 k31 k27 k23 k19 k15 k11 k7 k3 k32 k28 k24 k20 k16 k12 k8 k4 k47 k45 k43 k41 k39 k37 k35 k33 k48 k46 k44 k42 k40 k38 k36 k34 cdefef key scan counter (r06) key return check counter ( r0a ) ?
49 chapter 6 program description (3) custom code generation processing this program is set to output 0ah as the custom code and f5h as the custom code. specifically, 50h is set to data memory r4 as the custom code and afh is set to r5 as the custom code. caution in the nec format, the lsb is transmitted first, so values are set in opposite order to the bit string. (4) key data generation processing key data generation processing is described in (a) and (b) below. (a) bit configuration of key data key data consists of eight bits. each bit indicates a key source and key return status. to accommodate the eight types from k i/o0 to k i/o7 , the key scan counter uses the lsb of key data h and the high-order two bits of key data l when input is via k i0 to k i3 , and uses the high-order three bits of key data l when input is via s 0 and s 1 . the key return check counter accommodates the four types from k i0 to k i3 by using the low-order two bits of key data l and accommodates the two types s 1 and s 0 by using the lsb of key data l. when the first key input is detected, 0ch is set to key data h if the input is via s 0 and s 1 . this key data h is also used to determine the format used to generate the key data, as shown in figures 6-6 and 6- 7. as is described in (b) data code below, this key data is also used as an address for table reference. therefore, the key data is configured as shown in figures 6-6 and 6-7. figure 6-6. bit configuration of key data when input is via k i0 to k i3 1 0 1 ks2 ks1 ks0 kr1 kr0 bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 ke y data h ke y data l key scan counter key return check counter
50 chapter 6 program description figure 6-7. bit configuration of key data when input is via s 0 and s 1 (b) data code the data code can be calculated by using the key data obtained via key input processing (as shown in figures 6-6 and 6-7) as an address for table lookup. the table lookup method uses the contents of rom as a transmit code by setting 1h to the high-order four bits of control register 0 (p3) and by setting the key data to the data pointer (see figure 6-8). figure 6-8. configuration of data pointer example when key position is k26 (key input k i2 ) 1. key scan counter (r06) = eh key return check counter (r0a) becomes dh (see figure 6-5). 2. the low-order three bits of the key scan counter and the low-order two bits of the key return check counter are used to configure the key data, as was shown in figure 6-6. ? key scan counter 1 1 1 0 ? key return check counter 1 1 0 1 ? bit configuration of key data 1 0 1 1 1 0 0 1 - 3. set key data to data pointer. ? configuration of data pointer 0 0 0 1 1 0 1 1 1 0 0 1 ? 1b9h fixed as "0" dp 7 dp 6 dp 5 dp 4 dp 3 dp 2 dp 1 dp 0 fixed as "0" dp 9 dp 8 b7 b6 b5 b4 r 10 r 00 data pointer (dp) control register 0 (p3) ???????????????? ??? ???? ???? ???????????????? ????????? ????????? ????????????????????? ????????????????????? ????????????????????? 1100ks2ks1ks0kr0 bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 key data h key data l key scan counter key return check counter
51 chapter 6 program description the following table reference addresses are generated when a key is generated using one of the bit configurations shown in figures 6-6 and 6-7. as mentioned above, 1h is set to the high-order four bits of control register 0 (p3). ? key input: k i0 to k i3 , key position: k1 to k32 ... reference addresses = 1a0h to 1bfh ? key input: s 0 and s 1 , key position: k33 to k48 ... reference addresses = 1c0h to 1cfh ? key combination (k29 + k30, k29 + k31, k29 + k32) when a key combination has been confirmed, 9h is set to key data h. k29 + k30 ... reference address = 19dh k29 + k31 ... reference address = 19eh k29 + k32 ... reference address = 19fh
52 chapter 6 program description 6.2.2 detailed flow chart ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) clear status flag clear status flag set chattering counter for three times all k i/o outputs are high level halt mode (timer cancel) key48 on_chat keys_out set input mode for s 1 and s 0 initialize compare key data set key scan counter to eight times clear key on flag initialize key scan data set key return check counter to four times set key return check counter to two times key scan output 100 s wait work area ? p 11 key ret no_keys key input? key input? k i input? input via s 1 or s 0 ? key input processing set timer counter to 9 ms main main set 0ch to compare key data h work area ? p 01 to main processing to main processing s0s1calc: key ret0: a e i j q s t u r w f g h k l m n o p b c d ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) no yes yes yes no no no yes m
53 chapter 6 program description ******** key input processing ******** time9m equ 1ffh ;9.00ms(9.002ms) custm1 equ 050h ;custom code = 0ah custm2 equ 0afh ;custom code = f5h ;########## p u b l i c ########## public key48 ; ;########## e x t e r n ########## extrn main ;main routine ; ;########## s t a r t ########## key48: mov r0,#00ch (a) sets (0ch to) chattering counter (r 00 ) (3 count end at 0fh.) ;*********************************************** ; on chattering ;*********************************************** on_chat: stts #0101b (b) clears status flag out p0,#0ffh (c) sets all k i/o outputs to high level out p4,#033h (d) sets input mode for s 1 and s 0 halt #005h (e) halt mode: timer is canceled when count reaches 00h mov t,#time9m (f) sets timer counter. (9 ms = 1ffh) mov r9,#000h (g) initializes (sets to 00h) compare key data (r9) mov r6,#008h (h) (i) sets 8h to key scan counter (r 06 ) and sets 0h to clear key on flag (r 16 ) stts #1110b (j) determines when there is key input (via k i , s 0 , or s 1 ) jnf main if no key input, processing branches to main mov r8,#001h (k) initializes (sets 01h to) key scan data (r8) ;*********************************************** ; key scan ;*********************************************** keys_out: mov a,r08 out p00,a (l) outputs key scan data (p 0 ) mov a,r18 out p10,a ;++++++++++++++++++++++++++++++++++ ;++ 100- m s wait before key input ++ ;++++++++++++++++++++++++++++++++++ mov r2,#0e1h remark r2 is used to set immediate data (r 12 : 0eh, r 02 : 1h). mov rb,#0c3h remark rb is used to set immediate data (r 1b : 0ch, r 0b : 3h). nop (m) 100- m s wait before performing key input check nop nop nop ........................ ........................
54 chapter 6 program description ;*********************************************** ; key return check ;*********************************************** stts #1011b (n) determines whether or not there is key input. jnf no_keys if no key input, processing branches to no_keys. stts #0011b (o) determines whether input is via k i or s 0 and s 1 jnf s0s1calc if via s 0 and s 1 , processing branches to s0s1calc. ;******************************* ; ki data calculate ;******************************* in a,p01 rl a (p) when there is input via k i , it determines whether there is jc main also input via s 0 and s 1 . rl a if there is also input via s 0 or s 1 , a key error is detected jc main and it goes to main processing. mov a,r1b (q) initializes the key return check counter (r 0a ). mov r0a,a 0ch = 4 times (in this case, r 1b = 0ch). in a,p11 (r) the pin status (p 11 ) of k i is transferred to the accumulator. jmp key_ret0 ;******************************* ; s0,s1 data calculate ;******************************* s0s1calc: mov r9,#0c0h (s) a judgment value (0ch) for k33 to k48 (for input via s 0 and s 1 ) is set to the compare key data h (r 19 ). mov a,r12 mov r0a,a (t) initializes the key return check counter (r 0a ). 0eh = 2 times (in this case, r 12 = 0eh). in a,p01 (u) the pin status (p 01 ) of s 0 or s 1 is transferred to the accumulator. key_ret0: mov r10,a remark the accumulators value (p 00 or p 01 ) is stored in the work area. stts #0101b (v) clears status flag. .........................
55 chapter 6 program description ( ) ( ) ( ) ( ) ( ) ( ) m n l ( ) k ( ) ( ) ( ) o ( ) r q p shift work area one bit leftward clear high-order three bits of a set bits 3 and 1 of a is k29 the compare key data? compare key data h = 0ch set key on flag? set k29 on flag? key input? key_ret a ? key scan counter shift a two bits leftward compare key data l ? a compare key data h ? a a and key return check counter a or compare key data l compare key data l ? a clear low-order two bits of compare key data l a ? 0011b clear lsb of a a ? key scan counter shift a one bit leftward compare key data l ? a a ? 0001b main go to main processing krc_inc key_calc: ki_calc: kl_calc: no yes yes no yes no yes no yes no a b c ( ) e ( ) f ( ) i ( ) j ( ) g ( ) h ( ) s t u ( ) a ( ) ( ) d ( )
56 chapter 6 program description key_ret: mov a,r10 rlz a (a) shifts work area 1 (r 10 ) one bit leftward mov r10,a jnc krc_inc (b) determines whether or not key input exists (cy = 1). ;** key input exists ** if there is no key input, processing branches to krc_inc. mov a,r16 scaf (c) determines whether or not key has been pressed (combination key). jnc key_calc if no combination key (only one key) has been pressed, processing branches to key_calc. mov a,r13 scaf (d) determines whether or not the k29 on flag has been set. jnc main if it has been cleared, processing branches to main. mov a,#0100b xrl a,r19 scaf jnc main (e) determines whether or not the compare key data (r9) mov a,r09 matches k29s key data. xrl a,r0b if they do not match, processing branches to main. scaf jnc main ;******************************* ; key data calculate ;******************************* key_calc: mov a,r0b (f) determines whether or not the pressed key is between xrl a,r19 k33 and k48 (input via s 0 or s 1 ). scaf if a key between k1 and k32 has been pressed, jnc ki_calc processing branches to ki_calc. accumulator values ;** s0,s1 data calculation ** mov a,r06 (g) transfers key scan counter (r 06 ) ks3 ks2 ks1 ks0 to accumulator. rl a (h) shifts accumulator one bit ks2 ks1 ks0 ks3 leftward. anl a,r12 (i) clears the accumulators lsb. ks2 ks1 ks0 0 (in this case, r 12 = 0eh). mov r09,a (j) stores accumulator values in r 09 compare key data l (r 09 ). mov a,r02 (k) sets 0001b to accumulator. 0001 (in this case, r 02 = 1h). jmp kl_calc to kl_calc ; ;** ki data calculation ** ki_calc: mov a,r06 (l) transfers key scan data (r 06 ) to ks3 ks2 ks1 ks0 rl a accumulator. (m) shifts accumulator two bits leftward ks1 ks0 ks3 ks2 rl a mov r09,a (n) stores accumulator values in r 09 compare key data l (r 09 ). anl a,r02 (o) clears the high-order three bits of the 000ks2 accumulator. (in this case, r 02 = 1h) orl a,#1010b (p) sets bit 3 and bit 1 of accumulator. 101ks2 mov r19,a (q) stores accumulator values in r 19 compare key data h (r 19 ). mov a,r09 anl a,r1b (r) clears the low-order two bits of ks1 ks0 0 0 mov r09,a the compare key data l (r 1b ). (in this case, r 1b = 0ch) r 09 mov a,r0b (s) sets 0011b to accumulator. 0011 (in this case, r 0b = 3h) ........................... ........................ ........................... ........................ ....................... .............................. ...........................
57 chapter 6 program description accumulator values kl_calc: k i input anl a,r0a (t) for k i input, the low-order two 0 0 kr1 kr0 bits of the key return counter (r 0a ) is stored in the accumulator. s 0 or s 1 input for s 0 or s 1 input, the lsb is 0 0 0 kr0 stored in the accumulator. orl a,r09 (u) or processing of accumulator k i input values and compare key data l ks1 ks0 kr1 kr0 (r 09 ). s 0 or s 1 input ks2 ks1 ks0 kr0 mov r09,a (v) accumulator data is stored in compare key data l (r 09 ). r 09
58 chapter 6 program description compare key data h ? 9h increment key return check counter shift key scan data one bit leftward clear status flag increment key scan counter has the key on flag been set? key return check completed? key scan completed eight times? no_keys krc_inc 1 set key on flag keys_out key_data key_ret b d f g i a e h c ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) single_k: yes no yes no no yes
59 chapter 6 program description ;** key combination check ** mov a,r16 scaf (a) determines whether or not the key on flag (r 16 ) has been set. jnc single_k if it has been cleared, processing branches to single_k. mov a,#09h (b) sets 9h to compare key data h (r 19 ). mov r19,a single_k: mov a,#0fh (c) sets the key on flag (r 16 ) mov r16,a (at this point, the accumulator value is 0fh). krc_inc: mov a,r0a inc a (d) increments the key return check counter (r 0a ). mov r0a,a jnc key_ret (e) determines whether or not the key return check has been completed four times. if it has not, processing branches to key_ret. no_keys: stts #0101b (f) clears status flag. mov a,r06 inc a (g) increments key scan counter (r 06 ). mov r06,a jc key_data (h) determines whether or not the key scan has been mov a,r18 completed eight times. rl a if it has been completed, processing branches to key_data. mov r18,a mov a,r08 rl a (i) shifts the key scan data (r8) one bit leftward. mov r08,a jnc keys_out mov r8,#010h jmp keys_out ........................ ........................ ........................ ........................ ........................ ........................
60 chapter 6 program description ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) high-level output from k i/o (all pins) key data ? compare key data increment chattering counter confirmation key data ? key data has the key on flag been set? chattering count = first time has chattering occurred three times? confirmation key data = key data? is confirmation key data k29? key data = compare key data? key_data set k29 on flag is confirmation key data combination key data? clear k29 on flag clear continue flag data_set on_chat main to main processing continue flag 0h : do not continue 0fh: continue if k29 : k29 on flag = 0fh if not k29: k29 on flag = 0h yes no no yes yes no yes no yes no yes no yes no keycheck : k29check: kdat_set: data_set: a b c e f g h ( ) k ( ) l i j ( ) m ( ) n ( ) d
61 chapter 6 program description ;*********************************************** ; transmit key data = on chattering key data ?? ;*********************************************** key_data: out p0,#0ffh (a) sets all key scan output (via k i/o ) as high-level output. mov r8,#0f0h remark r8 is used for setting immediate data (r 16 : 0fh, r 08 : 0h). mov a,r16 scaf (b) determines whether or not the key on flag (r 16 ) has been set. jnc main if it has been cleared, processing branches to main. mov a,r00 xrl a,r0b (c) determines whether or not chattering processing is occurring scaf for the first time (0ch). (in this case, r 00 = #0011b.) jc keycheck if it is the first time, processing branches to keycheck. mov a,r14 xrl a,r18 remark in this case, r 16 = 0fh. xrl a,r19 scaf jnc main (d) determines whether or not the key data (r4) matches the xrl a,r04 compare key data (r9). xrl a,r09 (in this case, accumulator value = 0fh.) scaf if they do not match, processing branches to main. jnc main keycheck: mov a,r19 mov r14,a (e) stores compare key data (r9) in key data (r4). mov a,r09 mov r04,a mov a,r00 inc a (f) increments the chattering counter (r 00 ). mov r00,a scaf jnc on_chat (g) determines whether or not chattering processing has been completed three times. if it has not been completed three times, processing ;** key high check ** branches to on_chat. xrl a,r11 xrl a,r14 remark in this case, accumulator value = 0fh. scaf jnc kdat_set ;** key low check ** (h) determines whether or not the confirmation key data (r1) xrl a,r01 matches the key data (r4). xrl a,r04 (in this case, accumulator value = 0fh.) scaf if they do not match, processing branches to kdat_set. jc k29check if they match, processing branches to k29check. kdat_set: mov a,r14 mov r11,a (i) stores key data (r4) in confirmation key data (r1). mov a,r04 mov r01,a mov a,r08 (j) clears continue flag (r 03 ). (in this case, r 08 = 0h). mov r03,a k29check: mov a,#0100b xrl a,r11 scaf jnc data_k_chk (k) determines whether or not k29 has been pressed. mov a,r01 (in this case, r 0b = 3h). xrl a,r0b if a key other than k29 has been pressed, processing scaf branches to k29_flg. jnc k29_flg ...................... ...................... ...................... ...................... ...................... ...................... ...................... ......................
62 chapter 6 program description dbl_k_chk: mov a,#06h xrl a,r11 (l) determines whether or not the confirmation key data is scaf combination key data. jc data_set if it is combination key data, processing branches to data_set. mov a,r08 (m) sets 0h to the accumulator. (in this case, r 08 = 0h.) k29_flg: mov r13,a (n) clears the k29 on flag (in this case, the accumulator value = 0h). (o) sets the k29 on flag (in this case, the accumulator value = 0fh). ......................
63 chapter 6 program description custom code ? table data custom code ? table data data pointer ? confir- mation key data table reference data code ? table data data_set trns to transmission processin g (a) (b) (c) (d)
64 chapter 6 program description ;*********************************************** ; transmit data set ;*********************************************** data_set: ;** custom code ** mov r4,#custm1 (a) stores custom code (r4) in table data. ;** custom code ** mov r5,#custm2 (b) stores custom code (r5) in table data. ;** data code ** mov a,r11 mov r10,a (c) stores confirmation key data (r1) in data pointer (r0). mov a,r01 mov r00,a mov r6,@r0 (d) stores data code (r6) in table data. end .........................
65 chapter 6 program description 6.3 transmission processing transmission processing transmits custom code, custom code, data code, and data code stored in the data memory, using the nec-r format that was described in chapter 2 transmission waveform . the transmission method uses a data table to store transmission times sets the timer counter via a table reference operation. afterward, it enters halt mode (cancellation condition: timer) to enable transmission. a method such as that shown in figure 6-10 is used to ensure correct and simple time management. immediately after cancellation of halt mode, a similar method is used to set the transmission time data for the next transmission to the timer counter so that the transmission operation can be performed during a set time between halt modes. when carrier output is set to on (hereafter, this status is called h), the timer counters msb (output control bit) is set. when carrier output is set to off (hereafter, this status is called l), the timer counters msb (output control bit) is cleared. figure 6-9 shows the timer counters configuration. figure 6-9. configuration of timer counter figure 6-10. time management of timer counter the timers operation time can be calculated as [(setting + 1) 8/f x ]. when operating at 455 khz, mov t,#1ffh indicates that [(1ffh + 1) 8/(455 10 3 ) ? 9.00 ms] has been set. t 9 t 8 t 7 t 6 t 5 t 4 output control bit t 3 t 2 t 1 t 0 9-bit count register timer counter halt (timer) set timer halt (timer) set timer halt #005h mov t, #1ffh... sets 9.00 ms carrier output halt #005h ... halt mode until 9.00 ms has elapsed mov t, #07fh... sets 2.25 ms carrier output as off any processing (as long as processing time is less than 9 ms)
66 chapter 6 program description 6.3.1 description of processing transmission processing includes the following seven types of processing. ? initialization ? leader code transmission ? code transmission (custom code, custom code, data code, and data code) ? stop bit transmission ? frame space transmission ? transmission of second and subsequent frames ? off chattering elimination processing each of these types of processing is described below. (1) initialization the initialization procedure for transmission processing is described in (a) and (b) below. (a) the key off check counter (r07) is set to 10 times (= 05h). (b) the data 1 transmit counter is set to 0dfh (for 24 bits). table 6-5 describes the counter contents. the data 1 transmit counter is used to count the number of times bit data 1 is transmitted within custom code or custom code that can affect the frame space transmission time. the number of data 1 occurrences in the data code and data code is fixed (at eight) and therefore does not affect the frame space transmission time. table 6-5. description of data 1 transmit counter (r9) counter value data 1 transmit counter description d0h number of data 1 occurrences: 0 to 7 | this status does not exist since the number of data 1 occurrences in data code and e6h data code is fixed (at eight). e7h number of data 1 occurrences: 8 number of data 1 occurrences in custom code and custom code: 0 e8h number of data 1 occurrences: 9 to 16 | number of data 1 occurrences in custom code and custom code: 1 to 8 efh f0h number of data 1 occurrences: 17 to 24 | number of data 1 occurrences in custom code and custom code: 9 to 16 f7h
67 chapter 6 program description (2) leader code transmission the transmission method for the leader code is described in (a) to (f) below. (a) the table reference address (1d8h) for the leader code is set as follows. ? high-order address (0dh) is set to data pointer h (r10) ? low-order address (8h) of data 0 in bit data is set to data 0 (r08) (b) output data 0h for leader code is set to work area 2 (r1a). (c) a subroutine (bitout0f) is called to transmit the leader code as a one-bit transmission. (d) work area 2 (r1a) is shifted leftward and a bit judgment is performed. (e) the table reference address l for the judged bit is set to data pointer l to enable the transmission time to be set to the timer counter. (f) the leader code (h: 9.00 ms, l: 4.50 ms) is transmitted. (3) code transmission (custom code, custom code, data code, and data code) the code transmission method is described in (a) to (h) below. (a) the table reference addresses (1dah and 1dch) for bit data used for code transmission are set as follows. ? high-order address (0dh) is set to data pointer h (r10) ? low-order address (0ah) of data 0 in bit data is set to data 0 (r08) ? low-order address (0ch) of data 1 in bit data is set to data 1 (r18) (b) the following data is set to work area 2 (r1a) when each type of code is transmitted. ? custom code h (r14) ? custom code l (r04) ? custom code h (r15) ? custom code l (r05) ? data code h (r16) ? data code l (r06) ? data code h (r16 is fully inverted) ? data code l (r06 is fully inverted) (c) a subroutine is called to transmit the each type of code as a four-bit transmission. (d) work area 2 (r1a) is shifted leftward and a bit judgment is performed. if data 1 is judged, the number of data 1 occurrences is counted to enable frame space transmission. (e) the table reference address l for the judged bit is set to data pointer l to enable the transmission time to be set to the timer counter. (f) each type of code is transmitted. ? data 0 ... h: 0.56 ms, l: 0.56 ms ? data 1 ... h: 0.56 ms, l: 1.69 ms a key off check is performed during low level transmission of each bit. for a description of the key off check, see (7) off chattering elimination processing below. (g) steps (d) to (f) above are repeated until four bits have been transmitted. (h) steps (b) to (g) above are repeated until all transmissions from custom code h to data code l are completed.
68 chapter 6 program description (4) transmission of stop bit the method for transmitting stop bits is described in (a) to (f) below. (a) the table reference address (1deh) for the stop bit is set as follows. ? high-order address (0dh) is set to data pointer h (r10) ? low-order address (0eh) of data 0 in bit data is set to data 0 (r08) (b) output data 0h for stop bit is set to work area 2 (r1a). (c) a subroutine is called to transmit the stop bit as a one-bit transmission. (d) work area 2 (r1a) is shifted leftward and a bit judgment is performed. (e) the table reference address l for the judged bit is set to data pointer l to enable the transmission time to be set to the timer counter. (f) the stop bit (h: 0.56 ms, l: 3.00 ms) is transmitted. (5) frame space transmission the code transmission time differs between transmission of the data 1 and data 0 bit data, with variation in the range of 59.06 ms to 77.06 ms. therefore, when transmitting code, the frame space transmission time varies according to the number of data 1 occurrences. however, since the number of data 1 occurrences is fixed (at eight) within the data code and data code, the frame space transmission times are not affected when these types of code are transmitted. the number of data 1 occurrences in the custom code and custom code do affect frame space transmission times. the number of data 1 occurrences are counted during transmission to enable responses to changes in transmission times. the frame space transmission times can be adjusted based on the count values. for details of data 1 counts, see (3) code transmission above. table 6-6 lists frame space times correspond to the number of data 1 occurrences. since the maximum value that can be set to the timer counter is 9.00 ms, the frame space is divided into the three patterns shown in figure 6-11 before being transmitted. differences between times shown in table 6-6 and figure 6-11 are margins of error during code transmission (such as when the data 0 low level time of 0.565 is set as 0.56) which are absorbed by frame spaces.
69 chapter 6 program description table 6-6. frame space times corresponding to data 1 occurrences no. of data 1 transmission no. of data 1 transmission no. of data 1 transmission no. of data 1 transmission occurrences time (ms) occurrences time (ms) occurrences time (ms) occurrences time (ms) 8 48.940 13 43.315 18 37.690 23 32.065 9 47.815 14 42.190 19 36.565 24 30.940 10 46.690 15 41.065 20 35.440 11 45.565 16 39.940 21 34.315 12 44.440 17 38.815 22 33.190 remark since the number of data 1 occurrences in data code and data code is fixed (at eight), the data 1 values are never between 0 and 7. figure 6-11. method for dividing frame space transmission times (1/2) (a) when there are eight data 1 occurrences (data 1 transmission counter value: 0e7h) a: after transmitting the stop bit, the frame space is transmitted for 3.00 ms. b: a frame space for the time period corresponding to the number of data 1 occurrences (18.94 ms) is transmitted. c : if a key has been pressed and held, on chattering elimination processing (9.00 ms 3 times) is performed. in other cases, a frame space is transmitted for 27.00 ms. (b) when there are from 9 to 16 data 1 occurrences (data 1 transmission counter value range: 0e8h to 0efh) a: after transmitting the stop bit, the frame space is transmitted for 3.00 ms. b: a frame space for the time period corresponding to the number of data 1 occurrences (9.94 to 17.80 ms) is transmitted. c : if a key has been pressed and held, on chattering elimination processing (9.00 ms 3 times) is performed. in other cases, a frame space is transmitted for 27.00 ms. c b b 27.00 ms 0.94 ms 9.00 ms b a 9.00 ms 3.00 ms c b 27.00 ms 0.94 to 8.80 ms b a 9.00 ms 3.00 ms
70 chapter 6 program description figure 6-11. method for dividing frame space transmission times (2/2) (c) when there are from 17 to 24 data 1 occurrences (data 1 transmission counter value range: 0f0h to 0f7h) a: after transmitting the stop bit, the frame space is transmitted for 3.00 ms. b: a frame space for the time period corresponding to the number of data 1 occurrences (0.94 to 8.80 ms) is transmitted. c : if a key has been pressed and held, on chattering elimination processing (9.00 ms 3 times) is performed. in other cases, a frame space is transmitted for 27.00 ms. (6) transmission of second and subsequent frames until the current key is released or changed, code transmission of second and subsequent frames is repeated starting with the leader code in the same manner as for the first frame. this transmission method is described in (2) to (5) above. for a description of the key off check, see (7) off chattering elimination processing below. (7) off chattering elimination processing a key off check is performed during low level output of bit data. key off status is confirmed only when absence of key input (i.e., key off) has been judged for ten consecutive times during 34 times of low level output that includes the leader code and stop bit. if even one key input (key on) is detected during the ten consecutive times being checked, the ten-time counter is cleared and the count is restarted. if key off status is not confirmed during the entire 34-time check, the key is judged as being pressed and held. even if key off status is confirmed during transmission of one frame, initialization processing is not performed until at least two frames have been transmitted. figure 6-12. key off check during bit data transmission c b 27.00 ms 0.94 to 8.80 ms a 3.00 ms ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? key off check (up to 34 times)
71 chapter 6 program description 6.3.2 detailed flow chart note as part of the main routine, the output data for the leader code is set to the accumulator (a) and the same data is set to work area 2 (r1a) via the called subroutine (bitout0c). set key off check counter for ten times initialize data 1 transmission counter data 0 ? table data's address l work area 2 ? output data for leader code data 1, data 0 ? table data's address l trns bitout0f work area 2 ? custom code' h bitout0c work area 2 ? custom code' l work area 2 ? custom code h work area 2 ? custom code l bitout0c bitout0c bitout0c (b) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) k l m n o a b c d e f g h i j note note note note note data pointer h ? 0dh
72 chapter 6 program description ******** transmission processing ******** time9m equ 1ffh ;9.00ms(9.002ms) ;########## p u b l i c ########## ; ;########## e x t e r n ########## extrn main ;main routine extrn key48 ;key check routine ; ;########## s t a r t ########## trns: mov r7,#0f5h (a) sets the key off check counter (r 07 ) for ten times (= 5h). r 17 is used for immediate setting (r 17 = 0fh). mov r9,#0dfh (b) initializes (sets dfh to) the data 1 transmission counter (r9). ;*********************************************** ; leader code remark transmission of leader code (h: 9.00 ms, l: 4.50 ms) ;*********************************************** mov r0,#0d0h (c) sets the 0dh (high-order address of the table data for the bit data transmission time) to data pointer h. mov r8,#008h (d) sets the low-order address of the table data for the bit data transmission time to data 1 (r 18 ) and data 0 (r 08 ) (r 18 ? 0h, r 08 ? 8h). mov a,r18 (e) sets the output data (0h) for leader code to the accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0f (f) calls the bit output subroutine (for one-bit transmission: counter value = 0fh). ;*********************************************** ; custom code remark transmission of custom code (h: 0.56 ms, l: 0.56 ms or 1.69 ms) ;*********************************************** mov r8,#0cah (g) sets the low-order address of the table data for the custom code to data 1 (r 18 ) and data 0 (r 08 ) (r 18 ? ch, r 08 ? ah). mov a,r14 (h) sets output data h (r 14 ) for custom code to accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (i) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). mov a,r04 (j) sets output data l (r 04 ) for custom code to accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (k) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). ;*********************************************** ; custom code remark transmission of custom code (h: 0.56 ms, l: 0.56 ms or 1.69 ms) ;*********************************************** mov a,r15 (l) sets output data h (r 15 ) for custom code to accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (m) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). mov a,r05 (n) sets output data l (r05) for custom code to accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (o) calls the bit output subroutine (for four-bit transmission: counter value = 0ch).
73 chapter 6 program description note as part of the main routine, the output data for the leader code is set to the accumulator (a) and the same data is set to work area 2 (r1a) by the called subroutine (bitout0c). work area 2 ? data code h 2 bitout0c work area 2 ? data code l bitout0c work area 2 ? data code h full inversion of work area 2 bitout0c work area 2 ? data code l bitout0c data 0 ? table data's address l work area 2 ? stop bit's output data bitout0f (c) note note note note note ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) k l m a b c d e f g h i j full inversion of work area 2
74 chapter 6 program description ;*********************************************** ; data code remark transmission of data code (h: 0.56 ms, l: 0.56 or 1.69 ms) ;*********************************************** mov a,r16 (a) sets output data h (r 16 ) for the data code to accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (b) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). mov a,r06 (c) sets output data l (r 06 ) for the data code to accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (d) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). ;*********************************************** ; data code remark transmission of data code (h: 0.56 ms, l: 0.56 or 1.69 ms) ;*********************************************** mov a,r16 (e) sets output data h (r 16 ) for the data code to accumulator. xrl a,#0fh (f) the accumulators value is inverted to create output data for data code h. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (g) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). mov a,r06 (h) sets output data l (r 06 ) for the data code to accumulator. xrl a,#0fh (i) the accumulators value is inverted to create output data for data code l. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (j) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). ;*********************************************** ; stop bit remark transmits stop bit (h: 0.56 ms, l: 3.00 ms) ;*********************************************** mov r8,#00eh (k) sets the low-order address of table data having a stop bit carrier to data 0 (r 08 ). mov a,r18 (l) sets the output data (0h) for the stop bit to the accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0f (m) calls the bit output subroutine (for one-bit transmission: counter value = 0fh).
75 chapter 6 program description note if pressed and held, continue flag = 0fh. key_on: set timer counter to 9 ms clear status flag set timer counter to 9 ms clear status flag clear msb of data 1 transmit counter l data pointer l ? data 1 transmit counter l is frame space at least 9 ms? is frame space at least 18 ms? timer counter ? table data clear status flag 3 set continue flag frame space = 27 ms frame space = 27 ms pressed and held? key off? trns main key48 to main processing to key input processing halt mode (timer cancel) halt mode (timer cancel) halt mode (timer cancel) halt mode (timer cancel) yes no yes no no yes yes no note t9_under: ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) k l ( ) m s ( ) r a b c d e f g h i j ( ) n ( ) p ( ) o ( ) q
76 chapter 6 program description ;*********************************************** ; frame space remark frame space transmission (l: 30.94 ms to 48.94 ms) ;*********************************************** mov a,r19 (a) judges the number of bit data 1 occurrences for custom scaf code (16 bits) as eight or less. jc t9_under if nine or above, processing branches to t9_under. halt #005h (b) halt mode: canceled when time counter reaches 00h. mov t,#time9m (c) if eight or less, sets timer counter to 9 ms (= 1ffh). stts #0101b (d) clears status flag. mov a,r09 (e) judges the number of bit data 1 occurrences for custom rl a code (16 bits) as zero or not zero. jc t9_under if 1 to 8, processing branches to t9_under. halt #005h (f) halt mode: canceled when time counter reaches 00h. mov t,#time9m (g) if zero, sets timer counter to 9 ms (= 1ffh) again for a total transmission time of 18 ms. t9_under: stts #0101b (h) clears status flag. mov a,r09 (i) clears the msb of the data 1 transmit counter l (r 09 ). anl a,#0111b mov r00,a (j) sets value of data 1 transmit counter l (r 09 ) to data pointer l (r 00 ). halt #005h (k) halt mode: canceled when time counter reaches 00h. mov t,@r0 (l) performs table lookup to set a value from 0.940 ms to 8.815 ms according to the number of bit data 1 occur- rences counted by the timer counter. stts #0101b (m) clears status flag. mov a,r03 scaf (n) judges transmission of first frame (to check for continue status). jnc key_on if transmitting the first frame, processing branches to key_on. mov a,r07 scaf (o) if transmitting the second or subsequent frame (continue jnc key48 status), it judges whether a key off status occurs during the transmission. if continue status is detected, process- ing branches to key_48. ;** frame space = 27ms ** call fs_27ms (p) if a key off status is detected during bit data transmission, the remaining 27 ms of the frame space is output. halt #005h (q) halt mode: canceled when time counter reaches 00h. jmp main processing branches to initialization processing and main. ; key_on: mov a,r17 (r) sets continue flag (r 03 ) (in this case, r 17 = 0fh). mov r03,a ;** frame space = 27ms ** call fs_27ms (s) calls subroutine for 27-ms output. jmp trns processing branches to trns. ....................... ....................... ........................ ........................ ........................ ........................
77 chapter 6 program description shift work area 2 one bit leftward increment data 1 transmit counter h timer counter ? table data clear status flag increment data pointer l increment key off check counter clear status flag increment work counter timer counter ? table data increment data 1 transmit counter l bit data = 1? key off check completed 10 times? work counter? count completed? halt mode (timer cancellation) halt mode (timer cancellation) bitout0f ret work area 2 ? output data work counter ? 0fh data pointer l ? data 1 initialize key off check counter bitout0c work area 2 ? output data work counter ? 0ch data pointer l ? data 0 overflow in data 1 transmit counter l? key input? yes no yes no no yes no yes yes no bit_trans2: bit_trans1: bit_trns: bit_dat1: bitout: ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) n o ( ) p s ( ) r a b e f h i j k l m ( ) q ( ) ( ) c d ( ) g ( ) t ( ) u ( ) v ( ) w ( ) x ( ) y
78 chapter 6 program description ;************************************************* ;***** ***** ;***** transmit ***** ;***** subroutine : bit out ***** ;***** ***** ;************************************************* bitout0f: mov r1a,a (a) sets output data to work area 2 (r 1a ). mov a,#0fh (b) sets 0fh to accumulator to set the transmit bit counter to count one time. jmp bitout processing branches to bitout. ; bitout0c: mov r1a,a (c) sets output data to work area 2 (r 1a ). mov a,#0ch (d) sets 0ch to accumulator to set the transmit bit counter to count four times. bitout: mov r0a,a remark either 0fh or 0ch can be set to the transmit bit counter (r 0a ). mov a,r1a rl a (e) shifts the output data one bit leftward. mov r1a,a jc bit_dat1 (f) judges whether bit data value is 0 or 1. ;** bit data = 0 ** if it is 1, processing branches to bit_dat1. mov a,r08 (g) sets data 0 (r 08 ) to data pointer l (r 00 ). mov r00,a jmp bit_trns processing branches to bit_trns. ; ;** bit data = 1 **; bit_dat1: mov a,r18 (h) sets data 1 (r 18 ) to data pointer l (r 00 ). mov r00,a mov a,r09 inc a (i) increments data 1 transmit counter l (r 09 ). mov r09,a jnc bit_trns (j) if there is no overflow in data 1 transmit counter l (r 09 ), mov a,r19 processing branches to bit_trns. inc a (k) increments data 1 transmit counter h (r 19 ). mov r19,a bit_trns: halt #005h (l) halt mode: canceled when time counter reaches 00h. mov t,@r0 (m) performs table lookup to set transmit time data to timer counter. stts #0101b (n) clears status flag. mov a,r00 inc a (o) increments data pointer l (r 00 ). mov r00,a halt #005h (p) halt mode: canceled when time counter reaches 00h. mov t,@r0 (q) performs table lookup to set transmit time data to timer counter. mov t,r07 inc a (r) judges whether key off status is maintained during ten consecutive times. jc bit_trans2 if key off status is confirmed, processing branches to bit_trans2. stts #1110b (s) determines whether or not key input exists. jnf bit_trans1 if a key has been pressed and held, processing branches to bit_trans1. ;** key input exists ** mov r7,#0f5h (t) initializes (= 5h) the key off check counter (r 07 ) if key input exists even once during the (10-time) key off check. jmp bit_trans2 processing branches to bit_trans2. ; ...................... ...................... ...................... ...................... ...................... ...................... ...................... .....................
79 chapter 6 program description ;** no key input ** bit_trans1: inc a (u) increments key off check counter. mov r07,a bit_trans2: stts #0101b (v) clears status flag. mov a,r0a (w) increments transmit bit counter (r 0a ). inc a jnc bitout (x) determines whether or not the transmit bit count has been completed. if not completed, processing branches to bitout. ret (y) end of processing ; end ...................... ......................
80 chapter 6 program description set timer counter to 9 ms clear status flag set counter (a) to count three times completed three times? frame space = 27 ms ret increment counter halt mode (timer cancellation) yes no fs_27ms: fs_27ms0: ( ) ( ) ( ) ( ) a b c d ( ) e ( ) f ( ) g
81 chapter 6 program description ;************************************************* ;***** ***** ;***** frame space = 27ms ***** remark subroutine for outputting remaining 27 ms of frame space. ;***** subroutine : fs 27ms ***** ;***** ***** ;************************************************* fs_27ms: mov a,#0dh (a) sets counter (accumulator) to count three times (= 0dh). fs_27ms0: halt #005h (b) halt mode: canceled when time counter reaches 00h. mov t,#time9m (c) sets timer counter to 9 ms (= 1ffh). stts #0101b (d) clears status flag. inc a (e) increments counter (accumulator). jnc fs_27ms0 (f) determines whether or not three times have been counted. if they have not been counted, processing branches to fs_27ms0. ret (g) end of processing
[memo] 82
chapter 7 cautions on program revisions note the following caution points when modifying the key matrix or the number of keys. (1) when changing the number of keys from 48 to 40 or 32 ? delete the keys that are enclosed in broken lines in the following diagram (when doing so, if the s 0 and s 1 / led pins are left unconnected, the number of keys can be changed without modifying the main program itself. note set by the program for internal pull-down resistor. (2) in addition to the modification described in (1) above, the s 1 /led pin can be used as an led pin: ? delete the keys that are enclosed in broken lines in the following diagram. ? leave the s 0 pin unconnected. ? change the s 1 /led pin so that b2 (the bit that sets the i/o mode for the s 1 /led port) in the main programs control register 1 (p4) remains in output mode (bit value = 1). (in m pd6133 series products, setting the s 1 /led pin to output mode automatically eliminates internal pull-down resistance.) k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 note k i2 note k i1 note k i0 note k i/o6 k i/o7 s 0 note s 1 /led note rem v dd x out x in gnd reset k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 note k i2 note k i1 note k i0 note k i/o6 k i/o7 s 0 note s 1 /led note rem v dd x out x in gnd reset m pd6133 m pd6133 83
84 chapter 7 cautions on program revisions note set by the program for internal pull-down resistor. k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 note k i2 note k i1 note k i0 note k i/o6 k i/o7 s 0 note s 1 /led note rem v dd x out x in gnd reset pd6133 m pd6133 m k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 note k i2 note k i1 note k i0 note k i/o6 k i/o7 s 0 note s 1 /led note rem v dd x out x in gnd reset v dd
chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 01-002 source = main48.asm e stno loc. obj. m i source statement 1 ;********************************************************************* 2 ;*** *** 3 ;*** multi - purpose remote control transmitter system *** 4 ;*** *** 5 ;*** cpu : upd6133 series *** 6 ;*** cpu clock : 455khz *** 7 ;*** trans. code: nec-r format (48key) *** 8 ;*** version : 2.0 *** 9 ;*** programmer : nec ic microcomputer systems corporation *** 10 ;*** *** 11 ;*** copyright(c) nec corporation 1995 *** 12 ;*** copyright(c) nims corporation 1995 *** 13 ;********************************************************************* 14 eject 85
86 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 01-003 source = main48.asm e stno loc. obj. m i source statement 15 001c time05m equ 01ch ;0.5ms (0.510ms) 16 01ff damytime equ 512-1 ;9.00ms (= 17.582us * 512) 17 18 ;########## p u b l i c ########## 19 public main 20 ; 21 ;########## e x t e r n ########## 22 ; 23 24 ;########## s t a r t ########## 25 26 ; control register (p3) reset:03h 27 ;===============================================================; 28 ; d9 d8 ! d7 ! d6 ! d5 ! d4 ! d3 ! d2 ! d1 ! d0 ! ; 29 ; ! ! d.p.! d.p.! d.p.! tctl! cary! mod1! mod0! ; 30 ; test mode! ! ad10! ad9 ! ad8 ! ! ! ! ! ; 31 ;---------------------------------------------------------------; 32 ; ! 0 ! * ! * ! * ! 1/1 ! on ! fx,fx/8 ! 0 ; 33 ; set 0 !-----------------------------------!.fx/12(1/2)!----; 34 ; ! 0 ! * ! * ! * ! 1/2 ! off !,fx/12(1/3)! 1 ; 35 ;===============================================================; 36 37 ; control register (p4) reset:26h 38 ;===============================================================; 39 ; d9 d8 ! d7 ! d6 ! d5 ! d4 ! d3 ! d2 ! d1 ! d0 ! ; 40 ; ! ! ! ki !s0/s1! !s1/led! ki/0! s0 ! ; 41 ; ! ! ! pull! pull! ! mode ! mode! mode! ; 42 ;---------------------------------------------------------------; 43 ; ! 0 ! 0 ! off ! off ! 0 ! in ! in ! off ! 0 ; 44 ; x !------------------------------------------------!---; 45 ; ! 0 ! 0 ! on ! on ! 0 ! out ! out ! in ! 1 ; 46 ;===============================================================; 47 48 ;*********************************************** 49 ; control register initialize 50 ;*********************************************** 51 main: 52 0000 e6f8 efef out p0,#0ffh ;ki/o all high 53 0002 e6fc e3e3 out p4,#033h 54 0004 e6fb e1e3 out p3,#013h ;set data pointer (p3:d8,d9) 55 0006 e6ff f7ff mov t,#damytime 56 0008 e3f1 e0e5 stts #0101b ;clear status flag 57 58 ;*********************************************** 59 ; ram initialize routine 60 ;*********************************************** 61 000a e6e1 e0e0 mov r1,#000h ;final key data (r1) = 00h 62 000c e6e3 e0e0 mov r3,#000h ;k29 on flag (r13) , continuance flag (r03) = 00h 63 64 000e e2f1 e0e8 halt #008h ;stop mode (ki = high) 65 0010 e0e0 nop ;no operation command 66 0011 e6ff e0e7 mov t,#time05m ;set timer : 0.5ms 67 ; 68 end
87 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 02-002 source = key48.asm e stno loc. obj. m i source statement 1 ;************************************************* 2 ;***** ***** 3 ;***** upd6133 series key check ***** 4 ;***** trans. code: nec-r format (48key) ***** 5 ;***** ***** 6 ;************************************************* 7 01ff time9m equ 1ffh ;9.00ms (9.002ms) 8 0050 custm1 equ 050h ;custom code = 0ah 9 00af custm2 equ 0afh ;custom code = f5h 10 11 ;########## p u b l i c ########## 12 public key48 13 ; 14 15 ;########## e x t e r n ########## 16 extrn main ;main routine 17 ; 18 19 ;########## s t a r t ########## 20 key48: 21 0013 e6e0 e0ec mov r0,#00ch ;chattering counter (r00) = 3 times 22 ;*********************************************** 23 ; on chattering 24 ;*********************************************** 25 on_chat: 26 0015 e3f1 e0e5 stts #0101b ;clear status flag 27 0017 e6f8 efef out p0,#0ffh ;ki/o all high 28 0019 e6fc e3e3 out p4,#033h 29 001b e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 30 001d e6ff f7ff mov t,#time9m ;timer = 9.00ms 31 001f e6e9 e0e0 mov r9,#000h ;comparative key data (r9) = 00h 32 0021 e6e6 e0e8 mov r6,#008h ;key flag (r16) = 00h , key scan counter (r06) = 08h 33 0023 e3f1 e0ee stts #1110b ;with input key (ki or s0 or s1) ? 34 0025 eff1 e0e0 jnf main ; else main: (without input key) 35 ; then (with input key) 36 0027 e6e8 e0e1 mov r8,#001h ;key scan data (r8) initialize : 001h 37 38 ;*********************************************** 39 ; key scan 40 ;*********************************************** 41 keys_out: 42 0029 ffe8 mov a,r08 43 002a e5f8 out p00,a ;key scan data l (p00) output 44 002b fee8 mov a,r18 45 002c e4f8 out p10,a ;key scan data h (p10) output 46 ;+++++++++++++++++++++++++++++ 47 ;++ 100us wait ++ 48 ;+++++++++++++++++++++++++++++ 49 002d e6e2 eee1 mov r2,#0e1h ;set immediate data : r2 50 002f e6eb ece3 mov rb,#0c3h ;set immediate data : rb 51 0031 e0e0 nop 52 0032 e0e0 nop 53 0033 e0e0 nop 54 0034 e0e0 nop 55 ;***********************************************
88 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 02-003 source = key48.asm e stno loc. obj. m i source statement 56 : key return check 57 ;*********************************************** 58 0035 e3f1 e0eb stts #1011b ;with input key (ki or s0 or s1) ? 59 0037 eff1 e9e3 jnf no_keys ; else no_keys: (without input key) 60 ; then (with input key) 61 0039 e3f1 e0e3 stts #0011b ;with input ki (p11) ? 62 003b eff1 e4e9 jnf s0s1calc ; else s0s1calc: (with input ki) 63 ; then (without input ki) 64 ;******************************* 65 ; ki data calculate 66 ;******************************* 67 003d fff9 in a,p01 ;with input ki , does it have s0 or s1 ? 68 003e fcf3 rl a ;with input s0 and s1 , it judges multiple keys error , 69 003f ecf1 e0e0 jc main ; and then goes to main: ! 70 0041 fcf3 rl a 71 0042 ecf1 e0e0 jc main 72 73 0044 feeb mov a,r1b ;r1b = 0ch 74 0045 e5ea mov r0a,a ;key return check counter (r0a) = 4 times (=0ch) 75 0046 fef9 in a,p11 76 0047 e8f1 e4ee jmp key_ret0 77 ; 78 79 ;******************************* 80 ; s0,s1 data calculate 81 ;******************************* 82 s0s1calc: 83 0049 e6e9 ece0 mov r9,#0c0h 84 004b fee2 mov a,r12 ;r12 = 0eh 85 004c e5ea mov r0a,a ;set key return check counter (r0a) = 2 times (=0eh) 86 004d fff9 in a,p01 87 88 key_ret0: 89 004e e4e0 mov r10,a ;work (r10) = p11 or p01 90 004f e3f1 e0e5 stts #0101b ;clear status flag 91 key_ret: 92 0051 fee0 mov a,r10 93 0052 fef3 rlz a 94 0053 e4e0 mov r10,a 95 0054 edf1 e8ee jnc krc_inc ;with input key ? 96 ;** with input key ** ; else krc_inc: (without input key) 97 0056 fee6 mov a,r16 ; then (with input key) 98 0057 faf3 scaf ;key flag (r16) = 0fh ? 99 0058 edf1 e6e9 jnc key_calc ; else key_calc: (except for 0fh) 100 005a fee3 mov a,r13 ; then (= 0fh) 101 005b faf3 scaf ;k29 on flag (r13) = 0fh ? 102 005c edf1 e0e0 jnc main ; else main: (= except for 0fh) 103 ; then (= 0fh) 104 005e fff1 f4e0 mov a,#0100b 105 0060 f4e9 xrl a,r19 106 0061 faf3 scaf ;comparative key data = k29 (r19=0bh) ? 107 0062 edf1 e0e0 jnc main ; then main: (key = except for k29) 108 0064 ffe9 mov a,r09 ; else (key = k29) 109 0065 f5eb xrl a,r0b ;r0b = 03h 110 0066 faf3 scaf ;comparative key data = k29 (r09=0ch) ?
89 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 02-004 source = key48.asm e stno loc. obj. m i source statement 111 0067 edf1 e0e0 jnc main ; then dbl_k_chk: (key = except for k29) 112 113 ;******************************* 114 ; key data calculate 115 ;******************************* 116 key_calc: 117 0069 ffeb mov a,r0b ;r0b = 03h 118 006a f4e9 xrl a,r19 119 006b faf3 scaf ;comparative key data h (r19) = 0ch ? 120 006c edf1 e7e5 jnc ki_calc ; else ki_calc: (ki data) 121 ;** s0 or s1 data calculation **; then (s0 or s1 data) 122 006e ffe6 mov a,r06 ;acc <-- key scan counter (r06) 123 006f fcf3 rl a 124 0070 fae2 anl a,r12 ;r12 = 1110b 125 0071 e5e9 mov r09,a 126 0072 ffe2 mov a,r02 ;r02 = 01h 127 0073 e8f1 e8e1 jmp kl_calc 128 ; 129 ;** ki data calculation ** 130 ki_calc: 131 0075 ffe6 mov a,r06 ;acc <-- key scan counter(r06) 132 0076 fcf3 rl a 133 0077 fcf3 rl a ;left shift (2 times) 134 0078 e5e9 mov r09,a ;comparative key data l (r09) <-- acc 135 0079 fbe2 anl a,r02 ;acc and 0001b (r02=01h) 136 007a fdf1 fae0 orl a,#1010b ;acc or 1010b 137 007c e4e9 mov r19,a ;comparative key data h (r19) <-- acc 138 007d ffe9 mov a,r09 ;acc <-- comparative key data l (r09) 139 007e faeb anl a,r1b ;acc and 1100b (r1b=0ch) 140 007f e5e9 mov r09,a ;comparative key data l (r09) <-- acc 141 0080 ffeb mov a,r0b ;acc <-- 0011b (r0b=03h) 142 143 kl_calc: 144 0081 fbea anl a,r0a ;acc and key return check counter (r0a) 145 0082 fde9 orl a,r09 ;acc or comparative key data l (r09) 146 0083 e5e9 mov r09,a ;comparative key data l (r09) <-- acc 147 148 ;** double key check ** 149 0084 fee6 mov a,r16 150 0085 faf3 scaf ;key flag (r16) = 0fh ? 151 0086 edf1 e8eb jnc single_k ; else single_k (single key) 152 0088 fff1 f9e0 mov a,#09h ; then (double key) 153 008a e4e9 mov r19,a 154 single_k: 155 008b fff1 ffe0 mov a,#0fh 156 008d e4e6 mov r16,a 157 158 krc_inc: 159 008e ffea mov a,r0a 160 008f f4f3 inc a ;key return check counter (r0a) increment 161 0090 e5ea mov r0a,a ;end of key return check ? 162 0091 edf1 e5e1 jnc key_ret ; else key_ret: (continuous) 163 ; then (end) 164 165 no_keys:
90 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 02-005 source = key48.asm e stno loc. obj. m i source statement 166 0093 e3f1 e0e5 stts #0101b ;clear status flag 167 0095 ffe6 mov a,r06 168 0096 f4f3 inc a ;key scan counter (r06) increment 169 0097 e5e6 mov r06,a ;end of key scan number of 8 time ? 170 0098 ecf1 eae6 jc key_data ; then key_data: (end) 171 009a fee8 mov a,r18 ; else (continuous) 172 009b fcf3 rl a ;key scan data h (r18) shift 173 009c e4e8 mov r18,a 174 009d ffe8 mov a,r08 175 009e fcf3 rl a 176 009f e5e8 mov r08,a ;key scan data l (r08) shift --> cy ? 177 00a0 edf1 e2e9 jnc keys_out ; else keys_out: (key scan data a low rank) 178 00a2 e6e8 e1e0 mov r8,#010h ; then (key scan data a high rank) 179 00a4 e8f1 e2e9 jmp keys_out 180 ; 181 182 ;*********************************************** 183 ; transmit key data = on chattering key data ? 184 ;*********************************************** 185 key_data: 186 00a6 e6f8 efef out p0,#0ffh ;ki/o all high 187 00a8 e6e8 efe0 mov r8,#0f0h ;set immediate data : r8 188 00aa fee6 mov a,r16 189 00ab faf3 scaf ;key flag (r16) = 0fh ? 190 00ac edf1 e0e0 jnc main ; else main: (= except for 0fh) 191 00ae ffe0 mov a,r00 ; then (= 0fh) 192 00af f5eb xrl a,r0b ;r0b = #0011b 193 00b0 faf3 scaf ;chattering counter (r00) = 1 times (=0dh) ? 194 00b1 ecf1 ebee jc keycheck ; then keycheck: (= 0dh) 195 ; else (= 0e-0fh) 196 00b3 fee4 mov a,r14 197 00b4 f4e8 xrl a,r18 ;r18 = 0fh 198 00b5 f4e9 xrl a,r19 ;acc = 0fh 199 00b6 faf3 scaf ;key data h (r14) = comparative key data h (r19) 200 00b7 edf1 e0e0 jnc main ; else main: (unmatch) 201 ; then (match) 202 00b9 f5e4 xrl a,r04 ;acc = 0fh 203 00ba f5e9 xrl a,r09 204 00bb faf3 scaf ;key data l (r04) = comparative key data l (r09) 205 00bc edf1 e0e0 jnc main ; else main: (unmatch) 206 keycheck: ; then (match) 207 00be fee9 mov a,r19 208 00bf e4e4 mov r14,a ;key data h (r14) <-- comparative key data h (r19) 209 00c0 ffe9 mov a,r09 210 00c1 e5e4 mov r04,a ;key data l (r04) <-- comparative key data l (r09) 211 00c2 ffe0 mov a,r00 212 00c3 f4f3 inc a ;chattering counter(r00) increment 213 00c4 e5e0 mov r00,a 214 00c5 faf3 scaf ;end of chattering routine of 3 time ? 215 00c6 edf1 e1e5 jnc on_chat ; else on_chat: (= 0dh) 216 ;** key high check ** ; then (= 0e-0fh) 217 00c8 f4e1 xrl a,r11 ;acc = 0fh 218 00c9 f4e4 xrl a,r14 219 00ca faf3 scaf ;final key data h (r11) = key data h (r14) ? 220 00cb edf1 ede2 jnc kdat_set ; else kdat_set: (unmacth)
91 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 02-006 source = key48.asm e stno loc. obj. m i source statement 221 ;** key low check ** ; then (match) 222 00cd f5e1 xrl a,r01 ;acc = 0fh 223 00ce f5e4 xrl a,r04 224 00cf faf3 scaf ;final key data l(r01) = key data l (r04) ? 225 00d0 ecf1 ede8 jc k29check ; then k29check: (match) 226 kdat_set: ; else (unmatch) 227 00d2 fee4 mov a,r14 228 00d3 e4e1 mov r11,a ;final key data h (r11) <-- key data h (r14) 229 00d4 ffe4 mov a,r04 230 00d5 e5e1 mov r01,a ;final key data l (r01) <-- key data l (r04) 231 00d6 ffe8 mov a,r08 232 00d7 e5e3 mov r03,a ;continuance flag = 00h (r08=00h) 233 234 k29check: 235 00d8 fff1 f4e0 mov a,#0100b 236 00da f4e1 xrl a,r11 237 00db faf3 scaf ;final key data = k29 (r11=0bh) ? 238 00dc edf1 eee3 jnc dbl_k_chk ; then dbl_k_chk: (key = except for k29) 239 00de ffe1 mov a,r01 ; else (key = k29) 240 00df f5eb xrl a,r0b ;r0b = 03h 241 00e0 faf3 scaf ;final key data = k29 (r01=0ch) ? 242 00e1 ecf1 eeea jc k29_flg ; then k29_flg: (key = except for k29) 243 ; else (key = k29) 244 dbl_k_chk: 245 00e3 fff1 f6e0 mov a,#06h 246 00e5 f4e1 xrl a,r11 247 00e6 faf3 scaf ;final key data = k29+ k30 or k31 or k32 (r11=09h) ? 248 00e7 ecf1 eeeb jc data_set ; then data_set: (key = except for double key) 249 00e9 ffe8 mov a,r08 250 k29_flg: 251 00ea e4e3 mov r13,a ;k29 on flag = 00h (r08=00h) 252 ;*********************************************** 253 ; transmit data set 254 ;*********************************************** 255 data_set: 256 ;** custom code ** 257 00eb e6e4 e5e0 mov r4,#custm1 ;custom code(r4) <-- custom code 258 259 ;** custom code ** 260 00ed e6e5 eaef mov r5,#custm2 ;custom code(r5) <-- custom code 261 262 ;** data code ** 263 00ef fee1 mov a,r11 264 00f0 e4e0 mov r10,a ;data pointer h(r10) <-- final key data h(r11) 265 00f1 ffe1 mov a,r01 266 00f2 e5e0 mov r00,a ;data pointer l(r00) <-- final key data l(r01) 267 00f3 e7e6 mov r6,@r0 268 269 end total errors = 0 total warnings = 0 end of list
92 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 03-002 source = trans48.asm e stno loc. obj. m i source statement 1 ;************************************************* 2 ;***** ***** 3 ;***** upd6133 series transmit ***** 4 ;***** trans. code: nec-r format (48key) ***** 5 ;***** ***** 6 ;************************************************* 7 01ff time9m equ 1ffh ;9.00ms (9.002ms) 8 9 ;########## p u b l i c ########## 10 ; 11 12 ;########## e x t e r n ########## 13 extrn main ;main routine 14 extrn key48 ;key check routine 15 extrn fs_27ms ;frame space subroutine 16 ; 17 18 ;########## s t a r t ########## 19 trns: 20 00f4 e6e7 efe5 mov r7,#0f5h ;r17 : set immediate data (=0fh) 21 ;key off check counter (r07) = 10 times (=05h) 22 00f6 e6e9 edef mov r9,#0dfh ;data1 trans counter (r9) = dfh 23 ;*********************************************** 24 ; leader code 25 ;*********************************************** 26 00f8 e6e0 ede0 mov r0,#0d0h ;data pointer h (r10) = 0dh 27 00fa e6e8 e0e8 mov r8,#008h ;set table address l 28 00fc fee8 mov a,r18 ;output data (work) <-- 00h (r18) 29 00fd e6f2 e8f1 e5ff call bitout0f 30 31 ;*********************************************** 32 ; custom code 33 ;*********************************************** 34 0100 e6e8 ecea mov r8,#0cah ;set table address l 35 0102 fee4 mov a,r14 ;output data (work) <-- custom code h (r14) 36 0103 e6f2 e8f1 e6f4 call bitout0c 37 38 0106 ffe4 mov a,r04 ;output data (work) <-- custom code l (r04) 39 0107 e6f2 e8f1 e6f4 call bitout0c 40 41 ;*********************************************** 42 ; custom code 43 ;*********************************************** 44 010a fee5 mov a,r15 ;output data (work) <-- custom code h (r15) 45 010b e6f2 e8f1 e6f4 call bitout0c 46 47 010e ffe5 mov a,r05 ;output data (work) <-- custom code l (r05) 48 010f e6f2 e8f1 e6f4 call bitout0c 49 50 ;*********************************************** 51 ; data code 52 ;*********************************************** 53 0112 fee6 mov a,r16 ;output data (work) <-- data code h (r16) 54 0113 e6f2 e8f1 e6f4 call bitout0c 55
93 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 03-003 source = trans48.asm e stno loc. obj. m i source statement 56 0116 ffe6 mov a,r06 ;output data (work) <-- data code l (r06) 57 0117 e6f2 e8f1 e6f4 call bitout0c 58 59 ;*********************************************** 60 ; data code 61 ;*********************************************** 62 011a fee6 mov a,r16 ;output data (work) <-- data code h (r16) 63 011b f5f1 ffe0 xrl a,#0fh 64 011d e6f2 e8f1 e6f4 call bitout0c 65 66 0120 ffe6 mov a,r06 ;output data (work) <-- data code l (r06) 67 0121 f5f1 fee0 xrl a,#0fh 68 0123 e6f2 e8f1 e6f4 call bitout0c 69 70 ;*********************************************** 71 ; stop bit 72 ;*********************************************** 73 0126 e6e8 e0ee mov r8,#00eh ;set table address l 74 0128 fee8 mov a,r18 ;output data (work) <-- 00h (r18) 75 0129 e6f2 e8f1 e5ff call bitout0f 76 77 ;*********************************************** 78 ; frame space 79 ;*********************************************** 80 012c fee9 mov a,r19 81 012d faf3 scaf ;frame space > 9.00ms ? 82 012e ecf1 e3fe jc t9_under ; then t9_under: (more than 9.00ms) 83 ; else (less than 9.00ms) 84 0130 e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 85 0132 e6ff f7ff mov t,#time9m 86 0134 e3f1 e0e5 stts #0101b ;clear status flag 87 88 0136 ffe9 mov a,r09 89 0137 fcf3 rl a ;frame space > 18.00ms ? 90 0138 ecf1 e3fe jc t9_under ; then t9_under: (less than 18.00ms) 91 ; else (more than 18.00ms) 92 013a e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 93 013c e6ff f7ff mov t,#time9m 94 95 t9_under: 96 013e e3f1 e0e5 stts #0101b ;clear status flag 97 0140 fee9 mov a,r09 98 0141 fbf1 f7e0 anl a,#0111b 99 0143 e5e0 mov r00,a 100 0144 e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 101 0146 e7ff mov t,@r0 102 0147 e3f1 e0e5 stts #0101b ;clear status flag 103 104 0149 ffe3 mov a,r03 105 014a faf3 scaf ;continuously pressed key ? 106 014b edf1 e5f8 jnc key_on ; else key_on: (1st. frame) 107 014d ffe7 mov a,r07 ; then (since 2nd. frame) 108 014e faf3 scaf ;without input key ? 109 014f edf1 e1e3 jnc key48 ; then key48: (with input key) 110 ;** frame space = 27ms ** ; else (without input key)
94 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 03-004 source = trans48.asm e stno loc. obj. m i source statement 111 0151 extrn call fs_27ms 112 0154 e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 113 0156 e8f1 e0e0 jmp main 114 ; 115 key_on: 116 0158 fee7 mov a,r17 117 0159 e5e3 mov r03,a ;continuance flag (r03) = 0fh (r17=0fh) 118 ;** frame space = 27ms ** 119 015a extrn call fs_27ms 120 015d e8f1 efe4 jmp trns 121 ; 122 123 124 ;************************************************* 125 ;***** ***** 126 ;***** transmit ***** 127 ;***** subroutine : bit out ***** 128 ;***** ***** 129 ;************************************************* 130 bitout0f: 131 015f e4ea mov r1a,a ;set output data (1 bit output) 132 0160 fff1 ffe0 mov a,#0fh ;send bit counter = 1 times (=0fh) 133 0162 e8f1 e6f7 jmp bitout 134 ; 135 bitout0c: 136 0164 e4ea mov r1a,a ;set output data (4 bit output) 137 0165 fff1 fce0 mov a,#0ch ;send bit counter = 4 times (=0ch) 138 139 bitout: 140 0167 e5ea mov r0a,a ;send bit counter (r0a) = 0ch or 0eh or 0fh 141 142 0168 feea mov a,r1a 143 0169 fcf3 rl a 144 016a e4ea mov r1a,a ;bit data = 1 ? 145 016b ecf1 e7f1 jc bit_dat1 ; then bit_dat1: (bit data = 1) 146 ;** bit data = 0 ** ; else (bit data = 0) 147 016d ffe8 mov a,r08 ;set data pointer l (r00) <-- data0 (r08) 148 016e e5e0 mov r00,a 149 016f e8f1 e7fb jmp bit_trns 150 ; 151 ;** bit data = 1 **; 152 bit_dat1: 153 0171 fee8 mov a,r18 ;set data pointer l(r00) <-- data1 (r18) 154 0172 e5e0 mov r00,a 155 0173 ffe9 mov a,r09 156 0174 f4f3 inc a ;data 1 transmit counter l (r09) increment 157 0175 e5e9 mov r09,a ;data 1 transmit counter l (r09) = overflow ? 158 0176 edf1 e7fb jnc bit_trns ; else bit_trns: (data 1 transmit counter l <= 0fh) 159 0178 fee9 mov a,r19 ; then (data 1 transmit counter l > 0fh) 160 0179 f4f3 inc a ;data 1 transmit counter h(r19) increment 161 017a e4e9 mov r19,a 162 bit_trns: 163 017b e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 164 017d e7ff mov t,@r0 165 017e e3f1 e0e5 stts #0101b ;clear status flag
95 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 03-005 source = trans48.asm e stno loc. obj. m i source statement 166 0180 ffe0 mov a,r00 167 0181 f4f3 inc a ;data pointer l (r00) increment 168 0182 e5e0 mov r00,a 169 0183 e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 170 0185 e7ff mov t,@r0 171 172 0186 ffe7 mov a,r07 173 0187 f4f3 inc a ;key off check counter (r07) increment 174 0188 ecf1 e9f3 jc bit_trans2 ;key off check counter (r07) = end of 10 times ? 175 ; then bit_trans2: (end of 10 times) 176 ; else (less than 10 times) 177 018a e3f1 e0ee stts #1110b ;with input key ? 178 018c eff1 e9f2 jnf bit_trans1 ; else bit_trans1: (with input) 179 ;** with input key ** ; then (without input) 180 018e e6e7 efe5 mov r7,#0f5h ;key off check counter (r07) = 05h 181 0190 e8f1 e9f3 jmp bit_trans2 182 ; 183 ;** without input key ** 184 bit_trans1: 185 0192 e5e7 mov r07,a 186 187 bit_trans2: 188 0193 e3f1 e0e5 stts #0101b ;clear status flag 189 0195 ffea mov a,r0a 190 0196 f4f3 inc a ;send bit counter (r0a) increment 191 0197 edf1 e6f7 jnc bitout 192 0199 e8f2 ret 193 ; 194 end total errors = 0 total warnings = 0 end of list
96 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 04-002 source = dtable48.tbl e stno loc. obj. m i source statement 1 ;************************************************* 2 ;***** ***** 3 ;***** upd6133 series data table ***** 4 ;***** trans. code: nec-r format (48key) ***** 5 ;***** ***** 6 ;************************************************* 7 01ff time9m equ 1ffh ;9.00ms (9.002ms) 8 9 ;########## p u b l i c ########## 10 public datacode 11 public fs_27ms 12 ; 13 14 datacode: 15 ;************************************** 16 ;***** key data ***** 17 ;***** double key ***** 18 ;************************************** 19 019d org 19dh 20 ;** k29 + k30 ** 21 019d e0e9 dw 009h ;k29 + k30 : key data = 0dh 22 ;** k29 + k31 ** 23 019e e8e9 dw 089h ;k29 + k31 : key data = 0eh 24 ;** k29 + k32 ** 25 019f e4e9 dw 049h ;k29 + k32 : key data = 0fh 26 ; 27 28 ;************************************** 29 ;***** key data ***** 30 ;***** single key ***** 31 ;************************************** 32 01a0 org 1a0h 33 ;** k 1 - k16 ** 34 01a0 e0e0 dw 000h ;k 1 : key data = 20h 35 01a1 e8e0 dw 080h ;k 2 : key data = 21h 36 01a2 e4e0 dw 040h ;k 3 : key data = 22h 37 01a3 ece0 dw 0c0h ;k 4 : key data = 23h 38 01a4 e2e0 dw 020h ;k 5 : key data = 24h 39 01a5 eae0 dw 0a0h ;k 6 : key data = 25h 40 01a6 e6e0 dw 060h ;k 7 : key data = 26h 41 01a7 eee0 dw 0e0h ;k 8 : key data = 27h 42 01a8 e1e0 dw 010h ;k 9 : key data = 28h 43 01a9 e9e0 dw 090h ;k10 : key data = 29h 44 01aa e5e0 dw 050h ;k11 : key data = 2ah 45 01ab ede0 dw 0d0h ;k12 : key data = 2bh 46 01ac e3e0 dw 030h ;k13 : key data = 2ch 47 01ad ebe0 dw 0b0h ;k14 : key data = 2dh 48 01ae e7e0 dw 070h ;k15 : key data = 2eh 49 01af efe0 dw 0f0h ;k16 : key data = 2fh 50 ; 51 52 ;** k17 - k32 ** 53 01b0 e0e8 dw 008h ;k17 : key data = 30h 54 01b1 e8e8 dw 088h ;k18 : key data = 31h 55 01b2 e4e8 dw 048h ;k19 : key data = 32h
97 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 04-003 source = dtable48.tbl e stno loc. obj. m i source statement 56 01b3 ece8 dw 0c8h ;k20 : key data = 33h 57 01b4 e2e8 dw 028h ;k21 : key data = 34h 58 01b5 eae8 dw 0a8h ;k22 : key data = 35h 59 01b6 e6e8 dw 068h ;k23 : key data = 36h 60 01b7 eee8 dw 0e8h ;k24 : key data = 37h 61 01b8 e1e8 dw 018h ;k25 : key data = 38h 62 01b9 e9e8 dw 098h ;k26 : key data = 39h 63 01ba e5e8 dw 058h ;k27 : key data = 3ah 64 01bb ede8 dw 0d8h ;k28 : key data = 3bh 65 01bc e3e8 dw 038h ;k29 : key data = 3ch 66 01bd ebe8 dw 0b8h ;k30 : key data = 3dh 67 01be e7e8 dw 078h ;k31 : key data = 3eh 68 01bf efe8 dw 0f8h ;k32 : key data = 3fh 69 ; 70 ;** k33 - k48 ** 71 01c0 e0e4 dw 004h ;k33 : key data = 40h 72 01c1 e8e4 dw 084h ;k34 : key data = 41h 73 01c2 e4e4 dw 044h ;k35 : key data = 42h 74 01c3 ece4 dw 0c4h ;k36 : key data = 43h 75 01c4 e2e4 dw 024h ;k37 : key data = 44h 76 01c5 eae4 dw 0a4h ;k38 : key data = 45h 77 01c6 e6e4 dw 064h ;k39 : key data = 46h 78 01c7 eee4 dw 0e4h ;k40 : key data = 47h 79 01c8 e1e4 dw 014h ;k41 : key data = 48h 80 01c9 e9e4 dw 094h ;k42 : key data = 49h 81 01ca e5e4 dw 054h ;k43 : key data = 4ah 82 01cb ede4 dw 0d4h ;k44 : key data = 4bh 83 01cc e3e4 dw 034h ;k45 : key data = 4ch 84 01cd ebe4 dw 0b4h ;k46 : key data = 4dh 85 01ce e7e4 dw 074h ;k47 : key data = 4eh 86 01cf efe4 dw 0f4h ;k48 : key data = 4fh 87 ; 88 89 ;************************************** 90 ;***** frame space ***** 91 ;***** time data ***** 92 ;org 1d0h ***************************** 93 01d0 e7ed dt 1f4h ;counter:000 = 8.815ms (8.809ms) 94 01d1 e6ed dt 1b4h ;counter:001 = 7.690ms (7.683ms) 95 01d2 e5ed dt 174h ;counter:010 = 6.565ms (6.558ms) 96 01d3 e4ed dt 134h ;counter:011 = 5.440ms (5.433ms) 97 01d4 e3ed dt 0f4h ;counter:100 = 4.315ms (4.308ms) 98 01d5 e2ed dt 0b4h ;counter:101 = 3.190ms (3.182ms) 99 01d6 e1ed dt o74h ;counter:110 = 2.065ms (2.057ms) 100 01d7 e0ed dt 034h ;counter:111 = 0.940ms (0.932ms) 101 ; 102 103 ;************************************** 104 ;***** time data ***** 105 ;org 1d8h ***************************** 106 ;** leader code ** 107 01d8 ffff dt 3ffh ;carrier on : 9.000ms (9.002ms) 108 01d9 f3ff dt 0ffh ;carrier off : 4.500ms (4.501ms) 109 ;** bit data 0 ** 110 01da f8f7 dt 21fh ;carrier on : 0.560ms (0.563ms)
98 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 04-004 source = dtable48.tbl e stno loc. obj. m i source statement 111 01db f0f7 dt 01fh ;carrier off : 0.565ms (0.563ms) 112 ;** bit data 1 ** 113 01dc f8f7 dt 21fh ;carrier on : 0.560ms (0.563ms) 114 01dd f1f7 dt 05fh ;carrier off : 1.690ms (1.687ms) 115 ;** stop bit ** 116 01de f8f7 dt 21fh ;carrier on : 0.560ms (0.563ms) 117 01df e2fa dt 0a9h ;carrier off : 3.000ms (2.989ms) 118 ; 119 120 121 122 ;************************************************* 123 ;***** ***** 124 ;***** frame space = 27ms ***** 125 ;***** subroutine : fs 27ms ***** 126 ;***** ***** 127 ;************************************************* 128 129 fs_27ms: 130 01e0 fff1 fde0 mov a,#0dh ;counter(acc) = 3 times (=0dh) 131 fs_27ms0: 132 01e2 e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 133 01e4 e6ff f7ff mov t,#time9m ;timer = 9.00ms 134 01e6 e3f1 e0e5 stts #0101b ;clear status flag 135 01e8 f4f3 inc a ;more than 27ms ? 136 01e9 edf1 eef2 jnc fs_27ms0 ; else fs_27ms0: (frame space < 27ms) 137 01eb e8f2 ret ; then ret (frame space = 27ms) 138 ; 139 end total errors = 0 total warnings = 0 end of list
99 chapter 8 program list as6133 v1.01 << d6134 assemble list >> 21:25:49 06/03/96 page 05-002 source = option.asm e stno loc. obj. m i source statement 1 ;************************************** 2 ;***** set option ***** 3 ;************************************** 4 option 5 0000 0001 usep0c 6 endop 7 end total errors = 0 total warnings = 0 end of list
[memo] 100
pa rt 3 80-key program
[memo] 102
103 chapter 1 hardware configuration 1.1 application circuit example figure 1-1 shows an application circuit example. figure 1-1. application circuit example note the program is set for on-chip pull-down resistors. the k i , k i/o , s 0 , and s 1 /led pins are used to configure an 80-key key matrix. the transmission code is output via the rem pin with a carrier signal. table 1-1 lists the various pin functions. k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 note k i2 note k i1 note k i0 note + + k i/o6 k i/o7 s 0 note s 1 /led note rem v dd x out x in gnd reset pd6134 m key matrix (8 5) 2 = 80 keys
chapter 1 hardware configuration 104 table 1-1. pin functions pin name i/o function k i/o0 to k io7 output key source (active high) k i0 to k i3 input key return (active high) s 0 input key expansion s 1 /led input key return (active high) rem output infrared remote control signal (with carrier) 1.2 key matrix figure 1-2 illustrates the key matrix. the kn symbol (in which n = 1 to 80) indicates each keys position. figure 1-2. key matrix k i/o7 k i/o6 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k30 k26 k22 k18 k14 k10 k6 k2 k29 k25 k21 k17 k13 k9 k5 k1 k i3 k31 k27 k23 k19 k15 k11 k7 k3 k i1 k32 k28 k24 k20 k16 k12 k8 k4 k i0 k40 k39 k38 k37 k36 k35 k34 k33 s 1 k69 k65 k61 k57 k53 k49 k45 k41 k i3 k70 k66 k62 k58 k54 k50 k46 k42 k i2 k71 k67 k63 k59 k55 k51 k47 k43 k i1 s 0 = 0 s 0 = 1 (expansion) k72 k68 k64 k60 k56 k52 k48 k44 k i0 k80 k79 k78 k77 k76 k75 k74 k73 s 1 k i2
105 chapter 2 transmission waveform the transmission waveform that is output from the rem pin uses the nec-r (nec continuous) format. for description of the output data code, see chapter 4 output codes . 2.1 nec-r format figure 2-1 illustrates the nec-r format. figure 2-1. nec-r format ? transmission waveform ? transmission waveform for first frame ? transmission waveform for second and subsequent frames...same as transmission waveform for first frame ? bit data format ? carrier waveform 1 frame (108.00 ms) 1 frame (108.00 ms) transmission (two frames) for one key press when key is pressed and held leader code 8 bits custom code custom code data code data code 8 bits 8 bits 8 bits stop bit frame space 9.00 ms 4.50 ms 27.00 ms 0.56 ms 30.94 to 48.94 ms 18.00 to 36.00 ms 8.5 s m 26.5 s m fx = 455 khz carrier frequency: 38 khz duty factor: 1/3 0.56 ms 0.56 ms data ? data ? 1.125 ms 2.25 ms
106 [memo]
chapter 3 timing charts 3.1 timing charts for key input to rem output on chattering elimination processing checks for key input every 9.00 ms and if it detects on status three consecutive times, it determines that the key is on. on chattering elimination processing also checks for key status changes (between on and off or when the key is pressed and held). the off chattering elimination processing is described below. key off status is checked during low-level output of the bit data. during transmission of one frame (108 ms), key input is checked ten times with reference to the timing (34 times) of the low-level output from the rem pin. (1) if key off status is detected all ten times ... key off status is determined. (2) if key on status is detected during at least one of the ten times ... when key on status is detected, the check counter is cleared and key input is checked another ten times. (3) if (1) and (2) above do not determine key off status ... key press and hold status (key on status) is determined. even if key off status is determined during transmission of one frame, initialization processing does not begin until after the second or a subsequent frame is transmitted. 3.1.1 timing when a key is pressed and held figure 3-1 shows a timing chart for when a key is pressed and held. for details of on chattering elimination, see 6.2.1 (1) chattering elimination processing . 107
chapter 3 timing charts 108 figure 3-1. timing chart when key is pressed and held key input : actual key operation (manually pressing or releasing a key) software key : software-based key operation (key input judgment by program) rem output : transmission waveform output via rem pin on chattering : this refers to on chattering elimination processing. key input is checked three times at 9.00- ms intervals. off chattering : this refers to off chattering elimination processing. key input is checked throughout the (34-bit) bit space that includes the leader code and stop bit. frame space (1) : this frame space is used to maintain a one-frame time of 108.00 ms to modify the transmission time for custom codes. frame space (2) : when it is determined that the current frame is the first frame or that a key off status is in effect, frame space (2) is transmitted (during 27.00 ms) without any on chattering elimination processing. 3.1.2 timing during key off status figure 3-2 shows timing charts for when a key is released during a frame transmission. key input rem output on chattering off chattering 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms 27.50 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms frame space (1) frame space (2) off chattering frame space (1) on chattering software key
109 chapter 3 timing charts figure 3-2. timing chart for key off status (1/3) (1) when key is released during transmission of the first frame (key off status has been determined ten times consecutively during transmission of the first frame) ... key off status is confirmed during transmission of second frame (2) when key is released during transmission of the first frame (key off status has not been determined ten times consecutively during transmission of the first frame) ... key off status is confirmed during transmission of second frame key input : actual key operation (manually pressing or releasing a key) software key : software-based key operation (key input judgment by program) rem output : transmission waveform output via rem pin on chattering : this refers to on chattering elimination processing. key input is checked three times at 9.00- ms intervals. off chattering : this refers to off chattering elimination processing. key input is checked throughout the (34- bit) bit space that includes the leader code and stop bit. frame space (1) : this frame space is used to maintain a one-frame time of 108.00 ms to modify the transmission time for custom codes. frame space (2) : when it is determined that the current frame is the first frame or that a key off status is in effect, frame space (2) is transmitted (during 27.00 ms) without any on chattering elimination processing. rem output key input key off status on chattering 27.50 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms off chattering frame space (1) frame space (2) off chattering frame space (1) frame space (2) key on status key off status key off confirmation software key rem output key input key off status on chattering 27.50 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms off chattering frame space (1) frame space (2) off chattering frame space (1) frame space (2) key on status key off status key off status key off confirmation software key
chapter 3 timing charts 110 figure 3-2. timing chart for key off status (2/3) (3) when key is released during transmission of the second frame (key off status has been determined ten times consecutively during transmission of the second frame) ... key off status is confirmed during transmission of second frame (4) when key is released during transmission of the second frame (key off status has not been determined ten times consecutively during transmission of the second frame) ... key off status is confirmed by the key?s on chattering key input : actual key operation (manually pressing or releasing a key) software key : software-based key operation (key input judgment by program) rem output : transmission waveform output via rem pin on chattering : this refers to on chattering elimination processing. key input is checked three times at 9.00- ms intervals. off chattering : this refers to off chattering elimination processing. key input is checked throughout the (34- bit) bit space that includes the leader code and stop bit. frame space (1) : this frame space is used to maintain a one-frame time of 108.00 ms to modify the transmission time for custom codes. frame space (2) : when it is determined that the current frame is the first frame or that a key off status is in effect, frame space (2) is transmitted (during 27.00 ms) without any on chattering elimination processing. software key key input rem output key off status key on status key off status on chattering off chattering frame space (1) frame space (2) off chattering frame space (1) 0.94 to 18.94 ms 27.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms 27.50 ms 53.06 to 71.06 ms on chattering key off confirmation software key key input rem output key off status key off status key on status key off status on chattering off chattering frame space (1) frame space (2) off chattering frame space (1) 0.94 to 18.94 ms 27.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms 27.50 ms 53.06 to 71.06 ms frame space (2) key off confirmation
111 chapter 3 timing charts figure 3-2. timing chart for key off status (3/3) (5) when key is released during transmission of the first frame and is pressed again later ... key off cannot be confirmed since a key on status is detected during the second frame key input : actual key operation (manually pressing or releasing a key) software key : software-based key operation (key input judgment by program) rem output : transmission waveform output via rem pin on chattering : this refers to on chattering elimination processing. key input is checked three times at 9.00- ms intervals. off chattering : this refers to off chattering elimination processing. key input is checked throughout the (34- bit) bit space that includes the leader code and stop bit. frame space (1) : this frame space is used to maintain a one-frame time of 108.00 ms to modify the transmission time for custom codes. frame space (2) : when it is determined that the current frame is the first frame or that a key off status is in effect, frame space (2) is transmitted (during 27.00 ms) without any on chattering elimination processing. 3.2 timing charts of key operations 3.2.1 output patterns prior to key confirmation prior to key confirmation, on chattering elimination processing (9.00 ms 3 times = 27.00 ms) is performed and a key is confirmed when it has the same status all three times. key input confirmation is determined after at least 100 m s (at least six instructions when operating at 455 khz) has elapsed after the key source output pin goes to high level. figure 3-3 shows the detailed output patterns prior to key confirmation. software key key input rem output ke y off status on chattering off chattering 53.06 to 71.06 ms 27.50 ms 0.94 to 18.94 ms 27.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms frame space (1) frame space (2) off chattering frame space (1) on chattering ke y on status
chapter 3 timing charts 112 figure 3-3. output patterns prior to key confirmation (1/6) (1) when k4 is pressed a : when a key on status has been determined, the key return is checked and the key data is calculated. execution time ranges from approximately 1.32 to 2.02 ms. b : key input is checked. execution time is approximately 0.41 ms. c : this is the total output time for key scanning. this time varies according to the value of a. execution time ranges from approximately 4.18 to 4.88 ms. b a c 9.0 ms about 0.5 ms k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 s 0 s 1 stop cancel
113 chapter 3 timing charts figure 3-3. output patterns prior to key confirmation (2/6) (2) when k38 is pressed a : when a key on status has been determined, the key return is checked and the key data is calculated. execution time ranges from approximately 1.32 to 2.02 ms. b : key input is checked. execution time is approximately 0.41 ms. c : this is the total output time for key scanning. this time varies according to the value of a. execution time ranges from approximately 4.18 to 4.88 ms. b a c 9.0 ms about 0.5 ms k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 s 0 s 1 stop cancel
chapter 3 timing charts 114 figure 3-3. output patterns prior to key confirmation (3/6) (3) when k60 is pressed a : when a key on status has been determined, the key return is checked and the key data is calculated. execution time ranges from approximately 1.32 to 2.02 ms. b : key input is checked. execution time is approximately 0.41 ms. c : this is the total output time for key scanning. this time varies according to the value of a. execution time ranges from approximately 4.18 to 4.88 ms. b a c 9.0 ms about 0.5 ms k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 s 0 s 1 stop cancel
115 chapter 3 timing charts figure 3-3. output patterns prior to key confirmation (4/6) (4) when k29 is pressed along with valid combination key k32 (k29 + k32) a : when a key on status has been determined, the key return is checked and the key data is calculated. execution time ranges from approximately 1.32 to 2.02 ms. b : key input is checked. execution time is approximately 0.41 ms. c : this is the total output time for key scanning. this time varies according to the value of a. execution time ranges from approximately 4.18 to 4.88 ms. b a c 9.0 ms k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 s 0 s1
chapter 3 timing charts 116 figure 3-3. output patterns prior to key confirmation (5/6) (5) when k9 and k12 are pressed but are invalid due to an identical key source a : when a key on status has been determined, the key return is checked and the key data is calculated. execution time ranges from approximately 1.32 to 2.02 ms. b : key input is checked. execution time is approximately 0.41 ms. about 0.5 ms k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 s 0 s 1 ba stop cancel stop cancel stop cancel stop cancel about 0.3 ms
117 chapter 3 timing charts figure 3-3. output patterns prior to key confirmation (6/6) (6) when k10 and k16 are pressed but are invalid due to an identical key source a : when a key on status has been determined, the key return is checked and the key data is calculated. execution time ranges from approximately 1.32 to 2.02 ms. b : key input is checked. execution time is approximately 0.41 ms. about 0.5 ms k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 s 0 s 1 ba stop cancel stop cancel a stop cancel about 0.3 ms
chapter 3 timing charts 118 3.2.2 operation of combination key k29 is the combination key. there are three valid key combination pairs: k29 + k30, k29 + k31, and k29 + k32. for any pattern, a key combination is valid only when k29 is pressed first. in other words, if another key is pressed before or at the same time as k29, the key combination is not valid. figure 3-4 shows examples of key operations when a key combination is entered. figure 3-4. timing chart of key combination operation (1/2) (1) if another valid key (from k30 to k32) is pressed during transmission of the first frame of the k29 code, after the second frame of the k29 code is transmitted, the key combination becomes valid and the combinations code is transmitted. (2) if another valid key (from k30 to k32) is pressed during transmission of the third frame of the k29 code, after the k29 code and the third frame are transmitted, the key combination becomes valid and the combinations code is transmitted. rem output k29 key k30 key stop mode k29 on chattering transmission of first frame of the k29 code leader code k29 code transmission k29 + k30 code transmission stop cancel data code data code data code k29 off chattering transmission during remain- ing frame time k29 + k30 on chattering 27.50 ms 108.00 ms 9.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms 27.50 ms rem output k29 key k30 key stop mode k29 on chattering transmission of first and second frames of the k29 code 216.00 ms leader code k29 code transmission k29 + k30 code transmission stop cancel data code data code data code data code k29 off chattering transmis- sion during remaining frame time k29 + k30 on chattering 9.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms
119 chapter 3 timing charts figure 3-4. timing chart of key combination operation (2/2) (3) if k29 is pressed after another valid key (from k30 to k32) has been confirmed, a key check produces a key error and no code is transmitted (the key combination is not valid). (4) if another valid key (from k30 to k32) is pressed before k29 has been confirmed, a key check produces a key error and no code is transmitted (the key combination is not valid). rem output k29 key k30 key stop mode 27.50 ms 108.00 ms 9.00 ms 53.06 to 71.06 ms 0.94 to 18.94 ms 27.00 ms k29 on chattering transmission of first frame of the k30 code leader code k30 off chattering transmission during remain- ing frame time transmission during remain- ing frame time key error status k30 code transmission stop cancel data code data code rem output k29 key k30 key 27.00 ms 27.00 ms 27.00 ms 27.00 ms 27.00 ms 27.50 ms on chattering on chattering on chattering on chattering on chattering stop mode stop cancel key error status ? on chattering
chapter 3 timing charts 120 3.2.3 key transfer operation a key transfer operation can be performed when a valid combination key has been pressed. the key transfer operation is an operation that occurs when a second key is pressed before a previously pressed key is released. the operation for the second key is performed when the previous key is released. figure 3-5 shows the operation timing of a key transfer operation. figure 3-5. operation timing of key transfer operation (1) when a key transfer operation is performed to transfer to key b during transmission of the code for key a, a key check is performed after all of the code has been transmitted. a key error occurs if it is during a key combination period. when key a is released, key b becomes valid and its code is transmitted. (2) if the transfer to key b occurs before key a is confirmed, a key error occurs during the key check. a key error also occurs if it is during a key combination period. after key a is released, a key check is performed for key b. however, key b was released before it could be checked, so the check result is no key. key a 27.50 ms stop mode stop cancel no key key a valid keys a and b valid key b valid no key key a on chattering key b on chattering key a code transmission key a off chattering + remaining frame time key b code transmission stop mode frame time key b off chattering key error 117.00 ms 72.00 ms 27.00 ms 117.0 ms 53.06 to 71.06 ms 0.94 to 18.94 ms key b - 27.50 ms stop mode stop cancel no key key error no key on chattering 27.00 ms 27.00 ms 27.00 ms 27.00 ms 27.00 ms 27.00 ms 27.00 ms 27.00 ms key a key b stop mode
chapter 4 output codes table 4-1 lists the output codes. for output using the nec format, nec provides each customer with a custom code to avoid the risk of interfering with output from another remote control unit that outputs using the nec format. this program is set to output 0ah as the custom code and f5h as the custom code. contact your nec sales representative for information on obtaining a custom code. table 4-1. output codes (1/2) key no. custom custom data key no. custom custom data key no. custom custom data code code code code code code k1 0ah f5h 00h k28 0ah f5h 1bh k55 0ah f5h 36h k2 0ah f5h 01h k29 0ah f5h 1ch k56 0ah f5h 37h k3 0ah f5h 02h k30 0ah f5h 1dh k57 0ah f5h 38h k4 0ah f5h 03h k31 0ah f5h 1eh k58 0ah f5h 39h k5 0ah f5h 04h k32 0ah f5h 1fh k59 0ah f5h 3ah k6 0ah f5h 05h k33 0ah f5h 20h k60 0ah f5h 3bh k7 0ah f5h 06h k34 0ah f5h 21h k61 0ah f5h 3ch k8 0ah f5h 07h k35 0ah f5h 22h k62 0ah f5h 3dh k9 0ah f5h 08h k36 0ah f5h 23h k63 0ah f5h 3eh k10 0ah f5h 09h k37 0ah f5h 24h k64 0ah f5h 3fh k11 0ah f5h 0ah k38 0ah f5h 25h k65 0ah f5h 40h k12 0ah f5h 0bh k39 0ah f5h 26h k66 0ah f5h 41h k13 0ah f5h 0ch k40 0ah f5h 27h k67 0ah f5h 42h k14 0ah f5h 0dh k41 0ah f5h 28h k68 0ah f5h 43h k15 0ah f5h 0eh k42 0ah f5h 29h k69 0ah f5h 44h k16 0ah f5h 0fh k43 0ah f5h 2ah k70 0ah f5h 45h k17 0ah f5h 10h k44 0ah f5h 2bh k71 0ah f5h 46h k18 0ah f5h 11h k45 0ah f5h 2ch k72 0ah f5h 47h k19 0ah f5h 12h k46 0ah f5h 2dh k73 0ah f5h 48h k20 0ah f5h 13h k47 0ah f5h 2eh k74 0ah f5h 49h k21 0ah f5h 14h k48 0ah f5h 2fh k75 0ah f5h 4ah k22 0ah f5h 15h k49 0ah f5h 30h k76 0ah f5h 48h k23 0ah f5h 16h k50 0ah f5h 31h k77 0ah f5h 4ch k24 0ah f5h 17h k51 0ah f5h 32h k78 0ah f5h 4dh k25 0ah f5h 18h k52 0ah f5h 33h k79 0ah f5h 4eh k26 0ah f5h 19h k53 0ah f5h 34h k80 0ah f5h 4fh k27 0ah f5h 1ah k54 0ah f5h 35h 121
chapter 4 output codes 122 table 4-1. output codes (2/2) key no. custom code custom code data k29+k30 0ah f5h 90h k29+k31 0ah f5h 91h k29+k32 0ah f5h 92h
123 chapter 5 software configuration 5.1 general flow chart figure 5-1 shows a general flow chart of this program. figure 5-1. general flow chart chattering elimina- tion processing completed 3 times? initialize control register initialize ram and ports set transmit data (access table data) initialize ram used for transmission processing initialize ram used for key input processing key input? valid key? end key scanning? transfer of one frame completed? stop mode (key input cancel) start key scan output generate key data transmit leader code transmit custom code and custom code transmit data code and data code transmit stop bit transmit frame space yes yes yes yes yes yes no no no no no no chattering time setting (9 ms) halt mode (timer cancel) initialization processing transmission processing key input processing key off?
chapter 5 software configuration 124 5.2 program memory (rom) configuration the m pd6134s program memory (rom) consists of 1002 steps x 10 bits (the 22 steps from 3eah to 3ffh comprise the test program area). figure 5-2 shows a rom map for this program and figure 5-3 shows a data table map. figure 5-2. rom map 20ch 20bh 3eah 3e9h 200h 1ffh 19dh 19ch 19bh 0f8h 0f7h 013h 012h 000h address program memory test program area empty space frame space output subroutine data table (see figure 5-3) empty space transmit processing key input processing initialization 3ffh
125 chapter 5 software configuration figure 5-3. data table map time data frame space time data key data (k1 to k32) key data (k41 to k72) key data (k33 to k40) key data (k73 to k80) key data key combinations: k29 + k30, k29 + k31 k29 + k32 1a0h 19fh 1a8h 1a7h 1b8h 1b7h 1b0h 1afh 1c0h 1bfh 1e0h 1dfh 19dh address program memory 1ffh
chapter 5 software configuration 126 5.3 data memory (ram) configuration the data memory (ram) consists of 32 4-bit static ram, which is used to store processing data. some instructions enable ram contents to be manipulated in 8-bit units. r0 can function as a data pointer for rom addresses. rom contents can be accessed once a rom address is set to this data pointer. this is called a table reference for rom data. after reset, the value of r0 becomes 00h. rf can also be used as an address stack register. after reset, the values of r1 to rf are undefined. tables 5-1 to 5-3 show ram maps for the entire program (key input processing and transmission processing), for key input processing alone, and for transmission processing alone. table 5-4 describes ram usage. table 5-1. ram map h (1) l (0) r0 work area 1 chattering counter data pointer h data pointer l r1 confirmation key data h confirmation key data l r2 for immediate setting (0fh) for immediate setting (1h) r3 k29 on flag continue flag r4 key data h key data l custom code h custom code l r5 custom code h custom code l r6 key on flag key scan counter data code h data code l r7 for immediate setting (0fh) key off check counter r8 key scan data h key scan data l for immediate setting (0fh) for immediate setting (0h) data 1 data 0 r9 compare key data h compare key data l data 1 transmit counter h data 1 transmit counter l ra work area 2 key return check counter transmit bit counter rb for immediate setting (0ch) for immediate setting (3h) rc for immediate setting (08h) for immediate setting (3h) rd not used not used re not used not used rf address stack register
127 chapter 5 software configuration table 5-2. map of ram used for key input processing h (1) l (0) r0 work area 1 chattering counter data pointer h data pointer l r1 confirmation key data h confirmation key data l r2 for immediate setting (0fh) for immediate setting (1h) r3 k29 on flag continue flag r4 key data h key data l custom code h custom code l r5 custom code h custom code l r6 key on flag key scan counter data code h data code l r7 r8 key scan data h key scan data l for immediate setting (0fh) for immediate setting (0h) r9 compare key data h compare key data l ra key return check counter rb for immediate setting (0ch) for immediate setting (3h) rc for immediate setting (08h) for immediate setting (2h) rd not used not used re not used not used rf address stack register : used for transmission processing
chapter 5 software configuration 128 table 5-3. ram map used for transmission processing h (1) l (0) r0 data pointer h data pointer l work area 1 r1 r2 r3 continue flag r4 custom code h custom code l r5 custom code h custom code l r6 data code h data code l r7 for immediate setting (0fh) key off check counter r8 data 1 data 0 r9 data 1 transmit counter h data 1 transmit counter l ra work area 2 transmit bit counter rc rc not used not used rd not used not used re not used not used rf address stack register : used for key input processing
129 chapter 5 software configuration table 5-4. description of ram usage (1/3) name ram description data pointer r0 this pointer is used for indicating rom addresses. it is used when performing a table reference for rom data. chattering counter r00 this counter is used to count the number of times chattering occurs during key input processing. 0ch is set to this counter as the initial value to count three times. 0fh indicates completion of three times. work area 1 r10 this is a work area that is used to temporarily store data. confirmation key data r1 this is used to store confirmation key data after on chattering elimination processing has been completed. if other confirmation key data has already been stored, it is compared with the key data when chattering elimination processing is completed (r4). if the two sets of data match, the previous data is retained. if they do not match, the new key data (r4) is stored. for immediate setting (1h) r02 this is used to clear the high-order three bits. for immediate setting (0fh) r12 this is used to set 0fh. continue flag r03 during transmission processing, this flag is used to determine whether it is the first frame or a second or subsequent frame that is currently being transmitted. value description 0fh second or subsequent frame is being transmitted 0h first frame is being transmitted 0fh: set, 0h: clear k29 on flag r13 this flag is used to determine whether or not the k29 key (combination key) has been pressed. value description 0fh k29 key has been pressed 0h key other than k29 key has been pressed 0fh: set, 0h: clear key data r4 this is used to store the previous key data during on chattering. this data is compared with the compare key data (r9). if they match, the previous data is retained. if they do not match, the new compare key data (r9) is stored. custom code r4 this is used to store the custom code. custom code r5 this is used to store the custom code. data code r6 this is used to store the data code. key scan counter r06 this counter is used to count the number of key scans. since a count of eight is required, 8h (8 times) is set as the counters initial value.
chapter 5 software configuration 130 table 5-4. description of ram usage (2/3) name ram description key on flag r16 this flag is used to determine whether or not a key has been pressed. value description 0fh key has been pressed 0h key has been released 0fh: set, 0h: clear key off check counter r07 this counter is used to count the number of times key off status occurs during bit data transmission. since a count of ten is required, 5h is set as the initial value. when the value becomes 0fh (meaning ten continuous times of key off status), key off status is confirmed. if key off status is not determined at this time, the counter value is initialized. for immediate setting (0fh) r17 this is used to set various flags. key scan data r18 this is used to store output data for key scanning. data 0 r08 this is used to store the row addresses of time data (table data) for transmitting a data 1 r18 bit data value of 0 or 1. data 0: bit data 0 data 1: bit data 1 for immediate setting (0h) r08 this is used for flag setting. for immediate setting (0fh) r18 this is used for data inversion. the setting is 0fh. compare key data r9 this is used to store key data during on chattering. data 1 transmit counter r9 this counter is used to count the number of times bit data 1 is transmitted. key return check counter r0a this counter is used to calculate the key data based on the key return data. since a count of four is required for k i input and a count of one is required for input of s 1 , a initial value of 0ch (for four times) or 0eh (for one time) is set. transmit bit counter r0a this counter is used to set the required number of bits stored in work 2 (r1a) for bit transmissions. the counter counts from one to four times. setting description 0fh 1-bit transmission (for transmitting leader code and stop bit) 0eh 2-bit transmission (not used) 0dh 3-bit transmission (not used) 0ch 4-bit transmission (for transmitting custom code, custom code, data code, and data code)
131 chapter 5 software configuration table 5-4. description of ram usage (3/3) name ram description work area 2 r1a this is used to store output data for bit transmissions. for immediate setting (3h) r0b this is used for data judgments and for setting 3h. for immediate setting (0ch) r1b this is used for data judgments, for setting 0ch, for setting the high-order two bits, and for clearing the low-order two bits. for immediate setting (2h) r0c this is used for bit 1 judgments. for immediate setting (08h) r1c this is used for clearing the low-order three bits.
chapter 5 software configuration 132 5.4 flag maps table 5-5 describes flag operations during various types of processing. table 5-5. flag map (1) continue flag (r03) processing r03 initialization processing clear (0h) key input when the key data used for on chattering elimination clear (0h) processing processing differs from the confirmation key data from the previous on chattering elimination processing. transmission during frame space transmission of all frames judgment processing during frame space transmission of only one frame set (0fh) judgment: a judgment is made during this processing. (2) k29 on flag (r13) processing r13 initialization processing clear (0h) key input when key on flag has been set judgment processing when chattering has been completed three times and the set (0fh) confirmation key data is k29 when chattering has been completed three times and the clear (0h) confirmation key data is not k29, nor is there a valid key combination transmission processing C judgment: a judgment is made during this processing. : not used (3) key on flag (r16) processing r16 initialization processing C key input during ram initialization clear (0h) processing start of key return check judgment after key data calculation judgment during key return check or when there is key input set (0fh) after completion of key scanning (8 times) judgment transmission processing judgment: a judgment is made during this processing. : not used : used by other application
chapter 6 program description 6.1 initial settings microcontrollers used in infrared remote control transmitters generally use batteries as their power source. however, the lighting of infrared leds requires a large current consumption. the abrupt change in the power supply voltage when infrared leds are being lit can cause sudden changes in the contents of ram, ports, etc., which must be taken into consideration. to prevent operation faults that may occur as a result of sudden changes in the contents of ram, ports, etc., the program should be designed to reset data in ram, ports, etc., to the initial value after each transmission. 6.1.1 description of processing (1) port settings and control register initialization (a) k i/o port (p0) this is an 8-bit i/o port that is used for key scan output. this ports initial setting is ffh. all of the ports bits (k i/o1 to k i/o7 ) are set to high-level output. (b) control register 0 (p3) tables 6-1 and 6-2 list the contents of control register 0. the initial setting is 13h. the initial settings are shown in shaded areas in tables 6-1 and 6-2. 133
chapter 6 program description 134 table 6-1. control register 0 (p3) bit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 name C C dp (data pointer) tctl cary mod 1 mod 0 dp 9 dp 8 setting 0 fixed to 0 fixed to 0 0 0 1/1 on see table 6-2. 1 1 1 1/2 off after reset 00000011 b 0 and b 1 ....... specify the rem outputs carrier frequency and duty factor. b 2 ................... indicates presence/absence of carrier for frequency specified by b 0 and b 1 . 0 = on (with carrier), 1 = off (no carrier, high level) b 3 ................... changes the carrier frequency and the timer clock division ratio. 0 = 1/1 (carrier frequency: values set to b 0 and b 1 , timer clock: f x /8) 1 = 1/2 (carrier frequency: one half of values set to b 0 and b 1 , timer clock: f x /16) table 6-2. time clock and carrier frequency settings b3 b2 b1 b0 timer clock carrier frequency (duty factor) 0000 fx/8 fx (duty 1/2) 0 1 fx/8 (duty 1/2) 1 0 fx/12 (duty 1/2) 1 1 fx/12 (duty 1/3) 1 no carrier (high level) 1000 fx/16 fx/2 (duty 1/2) 0 1 fx/16 (duty 1/2) 1 0 fx/24 (duty 1/2) 1 1 fx/24 (duty 1/3) 1 no carrier (high level) b 4 and b 5 ....... specify the high-order two bits (dp 8 and dp 9 ) of the rom data pointer. remarks 1. : dont care 2. : initial setting (13h) 3. fx : system clock frequency
135 chapter 6 program description (c) control register 1 (p4) table 6-3 lists the contents of control register 1. the initial setting is 32h, which is shown in the shaded areas of the table. table 6-3. control register 1 (p4) bit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 name C C k i s 0 /s 1 Cs 1 /led k i/o s 0 pull-down pull-down mode mode mode setting 0 fixed to 0 fixed to 0 off off fixed to 0 s 1 in off 1 on on led out in when reset 00100110 b 0 ....... specifies the s 0 ports input mode. 0 = off mode (high impedance), 1 = in (input mode). b 1 ....... specifies the k i/o ports i/o mode. 0 = in (input mode), 1 = out (output mode). b 2 ....... specifies the s 1 /led ports i/o mode. 0 = s 1 (input mode), 1 = led (output mode) b 4 ....... specifies presence/absence of pull-down resistor when s 0 /s 1 port is in input mode. 0 = off (no pull-down), 1 = on (pull-down). b 5 ....... specifies presence/absence of pull-down resistor when k i port is in input mode. 0 = off (no pull-down), 1 = on (pull-down). remarks 1. all pull-down resistors are automatically switched off during output mode and off mode. 2. : initial setting (32h) (2) initialize ram the following ram contents are cleared to 0. ? confirmation key data (r1) ? continue flag (r03) ? k29 on flag (r13)
chapter 6 program description 136 (3) set stop mode table 6-4 lists the cancellation conditions for the halt instruction. the initial setting is 8h. when initialized, the (stop mode) cancellation conditions are set as shown in the shaded areas of the table. table 6-4. cancellation conditions for halt instruction halt instruction operand value mode setting precondition for settings cancellation condition b3 b2 b1 b0 0000 stop high-level output from all high-level input via at k i/o pins least one k i pin 0 1 1 stop high-level output from all high-level input via at k i/o pins least one k i pin 1 1 0 stop note 1 high-level output from k i/o0 pin high-level input via at least one k i pin 1 any combination of b 2 , b 1 , stop [the following conditions in addition to the above conditions] and b 0 above C high-level input via at least one pin between s 0 and s 1 note 2 0/1 1 0 1 halt C when timers down counter reaches 0 notes 1. when halt# 110b is set, use the k i/o0 pin and the k i pin to configure a key matrix so that an internal reset is executed whenever a runaway (control loss) condition occurs. 2. s 0 and/or s 1 (at least one of these pins that are used to cancel standby mode) must be set to input mode (an internal reset will not be executed if both are set to output mode). cautions 1. an internal reset is executed if the halt instruction is executed using operand values other than those specified above or when the precondition for halt instruction execution has not been met. 2. if stop mode is set when the timers down counter has not yet reached 0 (i.e., when the timer is operating), all 10 bits of the timers down counter and the timer output enable flags are cleared to zero and stop mode is set. 3. specify a nop instruction as the first instruction following cancellation of stop mode. remark : initial setting (8h) (4) after cancellation of stop mode, execute a nop instruction, then initialize the timer. the timers initial setting is 1ch (= 0.5 ms).
137 chapter 6 program description 6.1.2 detailed flow chart high-level output from all k i/o pins main main processing initialize ports initialize control registers p 13 ? 1h clear status flag set timer counter to 0.5 ms initialize ram nop instruction key80 to ke y input processin g stop mode (cancel key input) (a) (b) (c) (d) (f) (e) (g) (h)
chapter 6 program description 138 ******** initialization processing ******** time05m equ 01ch ; 0.5ms(0.510ms) damytime equ 512-1 ; 9.00ms ;########## p u b l i c ########## public main ; ;########## s t a r t ########## ;*********************************************** ; control register initialize ;*********************************************** main: out p0,#0ffh (a) sets all key scan outputs (k i/o ) to high level out p4,#032h (b) initializes ports s 0 : high impedance, s 1 : input mode, k i/o : output mode out p3,#013h (c) initializes control registers 0 and 1 (p 3 and p 4 ) with carrier, frequency: f x /12, duty factor: 1/3 tctl: 1/1, k i : with pull-down resistor s 0 and s 1 : with pull-down resistor data pointer: dp 8 and dp 9 = 01h (most significant position of table reference address) mov t,#damytime stts #0101b ;*********************************************** ; ram initialize routine ;*********************************************** (e) initializes ram mov r1,#000h confirmation key data (r1): 00h mov r3,#000h k29 on flag (r 13 ) and continue flag (r 03 ): 0h halt #008h (f) stop mode: canceled by high-level input via k i , s 0 , and s 1 nop (g) nop instruction mov t,#time05m (h) initializes timer value ; ich = 0.5 ms end (d) clears status flags -------------------------
139 chapter 6 program description 6.2 key input processing 6.2.1 description of processing key input processing includes chattering elimination processing, key scan processing, custom code generation processing, and key data generation processing. (1) chattering elimination processing when switching to key on or key off status, an unstable condition called chattering (on chattering or off chattering) exists until the key signal is stabilized as the high-level or low-level signal (see figure 6-1). since key input during chattering is also unstable, the program must provide a means of eliminating chattering. figure 6-1. chattering of key input signal figure 6-2 illustrates an example of chattering elimination processing (key on judgment example). at point <1>, key on status is detected when stop mode is canceled, and key input is checked during a set time period (from points <1> to <4>: 9.00 ms 3). in part (a) of the figure, key on status is detected at all check points, so the key signal is judged to be at high level at the software keys point <4>. the wait period (a + b + c) after key on status is detected at point <1> and before the software judges the signals high level status is called the chattering elimination period. in part (a), the chattering elimination period is a + b + c since the key input status is always on when checked. in part (b), the chattering elimination period is d + e + f + g + h. key on on chattering key confirmation off chattering key off
chapter 6 program description 140 figure 6-2. key on judgment when chattering occurs (a) (b) software key key input abc <1> <2> <3> <4> software key key input def gh <1> <2> <1> <2> <3> <4>
141 chapter 6 program description (2) key scan processing key scan processing is described in sections (a) and (b) below. (a) key matrix figure 6-3 shows an example of an 80-key key matrix. in this example, k i/o0 to k i/o7 are output ports that output key scan signals. these signals are captured (as key return signals) via input ports comprised of k i0 to k i3 , s 0 , and s 1 . since each of these key return signal input ports (k i0 to k i3 , s 0 and s 1 ) is connected to an internal pull-down resistor, low-level signals are input when no keys are being pressed. figure 6-3. 80-key key matrix note the program is set for on-chip pull-down resistor. (b) key scan to judge which of the keys in the 80-key key matrix is being pressed, the stts instruction is used to check for high-level signal input via k i0 to k i3 , s 0 , and s 1 . next, the key scan signals output ports (k i/o0 to k i/o7 ) are set to high level one at a time starting from k i/o0 to determine which output among k i/o0 to k i/o7 corresponds to the detected input. during the key scan processing part of the program, the key scan counter (key source position) and key return check counter (key return position) are used to detect the key data (key position). figure 6-5 shows the correspondence between key data and the values of these two counters. k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 n ote k i2 note k i1 note k i0 note k i/o6 k i/o7 s 0 note s 1 /led note pd6134 key matrix (8 5) 2 = 80 keys m
chapter 6 program description 142 for description of the key datas bit configuration in data memory, see (4) (a) bit configuration of key data . when performing a key scan, factors such as stray capacitance in the keyboard and key source delay due to line impedance must be taken into consideration. therefore, this program waits for about 100 m s (six steps when at 455 khz) following high-level output before capturing the key input. figure 6-4. key matrix figure 6-5. key data (key position) k i/o7 k i/o6 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k30 k26 k22 k18 k14 k10 k6 k2 k29 k25 k21 k17 k13 k9 k5 k1 k i3 k31 k27 k23 k19 k15 k11 k7 k3 k i1 k32 k28 k24 k20 k16 k12 k8 k4 k i0 k40 k39 k38 k37 k36 k35 k34 k33 s 1 k69 k65 k61 k57 k53 k49 k45 k41 k i3 k70 k66 k62 k58 k54 k50 k46 k42 k i2 k71 k67 k63 k59 k55 k51 k47 k43 k i1 s 0 = 0 s 0 = 1 (expansion) k72 k68 k64 k60 k56 k52 k48 k44 k i0 k80 k79 k78 k77 k76 k75 k74 k73 s 1 k i2 cdef f k30 k26 k22 k18 k14 k10 k6 k2 k29 k25 k21 k17 k13 k9 k5 k1 k31 k27 k23 k19 k15 k11 k7 k3 k32 k28 k24 k20 k16 k12 k8 k4 k40 k39 k38 k37 k36 k35 k34 k33 k69 k65 k61 k57 k53 k49 k45 k41 k70 k66 k62 k58 k54 k50 k46 k42 k71 k67 k63 k59 k55 k51 k47 k43 k72 k68 k64 k60 k56 k52 k48 k44 k80 k79 k78 k77 k76 k75 k74 k73 f e d c b a 9 8 cdef f key scan counter (r06) key return ? check counter (r0a)
143 chapter 6 program description (3) custom code generation processing this program is set to output 0ah as the custom code and f5h as the custom code. specifically, 50h is set to data memory r4 as the custom code and afh is set to r5 as the custom code. caution in the nec format, the lsb is transmitted first, so values are set in opposite order to the bit string. (4) key data generation processing key data processing is described in (a) and (b) below. (a) bit configuration of key data key data consists of eight bits. each bit indicates a key source or key return status. to accommodate the eight types from k i/o0 to k i/o7 , the key scan counter uses the lsb of key data h and the high-order two bits of key data l when input is via k i0 to k i3 , and uses the low-order three bits of key data l when input is via s 1 . the key return check counter accommodates the four types from k i0 to k i3 by using the low-order two bits of the key data. for input via s 1 , there is only one type, so the key return check counter is not used. the data from key expansion pin s 0 uses bit 1 of the key data h if input is via k i0 to k i3 and uses the msb of key data l if input is via s 1 . when the first key input is detected, 0bh is set to key data h if the input is from other than k i (such as input via s 1 ). this key data h is also used to determine the format used to generate the key data, as shown in figures 6-6 and 6-7. as is described in (b) data code below, this key data is also used as an address for table reference. therefore, the key data is configured as shown in figures 6-6 and 6-7. figure 6-6. bit configuration of key data when input is via k i0 to k i3 11s 0 ks2 ks1 ks0 kr1 kr0 bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 ke y data h ke y data l key scan counter key return check counter
chapter 6 program description 144 figure 6-7. bit configuration of key data when input is via s 1 (b) data code the data code can be calculated by using the key data obtained via key input processing (as shown in figures 6-6 and 6-7) as an address for table reference. the table reference method uses the contents of rom as a transmit code by setting 1h to the high-order four bits of control register 0 (p3) and by setting the key data to the data pointer (see figure 6-8). figure 6-8. configuration of data pointer example when key position is k26 (key input k i2 ) 1. key scan counter (r06) becomes eh key return check counter (r0a) becomes 0h (see figure 6-5). 2. the low-order three bits of the key scan counter and the low-order two bits of the key return check counter are used to configure the key data, as was shown in figure 6-6. ? key scan counter 1 1 1 0 ? key return check counter 1 1 0 1 ? bit configuration of key data 1 1 0 1 1 0 0 1 s 0 = 0 3. set key data to data pointer. ? configuration of data pointer 0 0 0 1 1 1 0 1 1 0 0 1 ? 1 d 9 h 1011s 0 ks2 ks1 ks0 bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 key data h key data l key scan counter fixed to "0" dp 7 dp 6 dp 5 dp 4 dp 3 dp 2 dp 1 dp 0 fixed to "0" dp 9 dp 8 b7 b6 b5 b4 r 10 r 00 data pointer (dp) control register 0 (p3)
145 chapter 6 program description the following table reference addresses are generated when a key is generated using one of the bit configurations shown in figures 6-6 and 6-7. as mentioned above, 1h is set to the high-order four bits of control register 0 (p3). ? key input: k i0 to k i3 , key position: k1 to k32 (when s 0 = 0) ... reference addresses = 1c0h to 1dfh ? key input: k i0 to k i3 , key position: k41 to k72 (when s 0 = 1) ... reference addresses = 1e0h to 1ffh ? key input: s 1 , key position: k33 to k40 (when s 0 = 0) ... reference addresses = 1b0h to 1b7h ? key input: s 1 , key position: k73 to k80 (when s 0 = 1) ... reference addresses = 1b8h to 1bfh ? key combination (k29 + k30, k29 + k31, k29 + k32) when a key combination has been confirmed, 9h is set to key data h. k29 + k30 ... reference address = 19dh k29 + k31 ... reference address = 19eh k29 + k32 ... reference address = 19fh
chapter 6 program description 146 6.2.2 detailed flow chart clear status flag clear status flag set immediate data (data memory: rc) all k i/o outputs are high level halt mode (timer cancel) key80 on_chat keys_out set input mode for s 1 and s 0 initialize compare key data set key scan counter to eight times clear key on flag initialize key scan data set key return check counter to four times set key return check counter to one time key scan output 100- s wait work area ? p 11 key ret no_keys key input? key input? k i input? input via s 1 ? key input processing set timer counter to 9 ms main main set 0bh to compare key data h work area ? p 01 to main processing to main processing s0s1calc: key ret0: (b) set chattering counter for three times (a) (f) (j) (n) (r) (t) (u) (v) (s) (w) (l) (m) (q) (p) (o) (k) (g) (h) (i) (c) (d) (e) no yes yes yes no no no yes m
147 chapter 6 program description ******** key input processing ******** time9m equ 1ffh ; 9.00ms(9.002ms) custm1 equ 050h ; custom code = 0ah custm2 equ 0afh ; custom code = f5h ;########## p u b l i c ########## public key80 ; ;########## e x t e r n ########## extrn main ; main routine ; ;########## s t a r t ########## key80: mov r0,#00ch (a) sets (0ch to) chattering counter (r 00 ) (three times count ends at 0fh.) mov rc,#082h (b) use rc to set immediate data (r 1c = 8h, r 0c = 2h) ;*********************************************** ; on chattering ;*********************************************** on_chat: stts #0101b (c) clears status flag out p0,#0ffh (d) sets all k i/o outputs to high level out p4,#033h (e) sets input mode for s 1 and s 0 halt #005h (f) halt mode: timer is canceled when count reaches 00h mov t,#time9m (g) sets timer counter. (9 ms = 1ffh) mov r9,#000h (h) initializes (sets to 00h) compare key data (r 9 ) mov r6,#008h (i) (j) sets 8h to key scan counter (r 06 ) and sets 0h to clear key on flag (r 16 ) stts #1110b (k) determines when there is key input (via k i , s 0 , or s 1 ) jnf main if no key input, processing branches to main. mov r8,#001h (l) initializes (sets 01h to) key scan data (r 8 ) ;*********************************************** ; key scan ;*********************************************** keys_out: mov a,r08 out p00,a (m) outputs key scan data (p 0 ) mov a,r18 out p10,a ;+++++++++++++++++++++++++++++ ;++ 100- m s wait before key input ++ ;+++++++++++++++++++++++++++++ mov r2,#0f1h remark r2 is used to set immediate data (r 12 : 0fh, r 02 : 1h). mov rb,#0c3h remark r8 is used to set immediate data (r 1b : 0ch, r 0b : 3h). nop (n) 100- m s wait before performing key input check nop nop nop ------------------------------ ------------------------------
chapter 6 program description 148 ;*********************************************** ; key return check ;*********************************************** stts #1011b (o) determines whether or not there is key input. jnf no_keys if no key input, processing branches to no_keys. stts #0011b (p) determines whether input is via k i or s 0 and s 1 . jnf s0s1calc if via s 0 and s 1 , processing branches to s0s1calc. ;******************************* ; ki data calculate ;******************************* in a,p01 rl a (q) when there is input via k i , it determines whether there is also input via s 1 . jc main if there is also input via s 1 , a multiple combination key error is detected and it goes to main processing. mov a,r1b (r) initializes the key return check counter (r 0a ). mov r0a,a 0ch = 4 times (in this case, r 1b = 0ch). in a,p11 (s) the pin status (p 11 ) of k i is transferred to the jmp key_ret0 accumulator. ;******************************* ; s0,s1 data calculate ;******************************* s0s1calc: mov r9,#0b0h (t) a judgment value (0bh) for k33 to k40 and k73 to k80 (for input via s 0 and s 1 ) is set to the compare key data h (r 19 ). mov a,r12 mov r0a,a (u) initializes the key return check counter (r 0a ). 0fh = 1 time (in this case, r 12 = 0fh). in a,p01 (v) the pin status (p 01 ) of s 0 or s 1 is transferred to the accumulator. key_ret0: mov r10,a remark the accumulators value (p 00 or p 01 ) is stored in the work area. stts #0101b (w) clears status flag. ------------------------------
149 chapter 6 program description shift work area one bit leftward clear high-order three bits of a clear low-order three bits of a set high-order two bits of a set key on flag? set k29 on flag? is k29 the compare key data? compare key data h = 0bh key input? key_ret (a) a ? key scan counter shift a two bits leftward compare key data l ? a a ? key scan counter clear msb of a compare key data l ? a a ? work area 1 compare key data h ? a a ? p 01 shift a three bits leftward krc_inc main go to main processing kl_calc (g) (h) (i) (j) (k) (l) (a) (m) (n) (o) (p) (q) (r) (s) (f) (e) (d) (c) (b) no yes yes no yes no yes no yes no key_calc: ki_calc:
chapter 6 program description 150 key_ret: mov a,r10 rlz a (a) shifts work area 1 (r 10 ) one bit leftward mov r10,a jnc krc_inc (b) determines whether or not key input exists (cy = 1). ;** key input exists ** if there is no key input, processing branches to krc_inc. mov a,r16 scaf (c) determines whether or not key has been pressed (combination key). jnc key_calc if no combination key (only one key) has been pressed, processing branches to key_calc. mov a,r13 scaf (d) determines whether or not the k29 on flag has been set. jnc main if it has been cleared, processing branches to main. mov a,r0c remark in this case, r 0c = 2h. xrl a,r19 scaf jnc main (e) determines whether or not the compare key data (r9) matches k29s key data. mov a,r09 if they do not match, processing branches to main. xrl a,r0b scaf jnc main ;******************************* ; key data calculate ;******************************* key_calc: mov a,#04h xrl a,r19 (f) determines whether or not the pressed key is between k33 and k40 scaf or k73 and k80 (input via s 0 or s 1 ). jnc ki_calc if a key between k1 and k32 and or k41 and k72 has been pressed, ;** s1 data calculation ** processing branches to ki_calc. accumulator values mov a,r06 (g) transfers key scan counter (r 06 ) ks3 ks2 ks1 ks0 to accumulator. anl a,#0111b (h) clears the accumulators msb. 0 ks2 ks1 ks0 mov r09,a (i) stores accumulator values in a cc ? r 09 compare key data l (r 09 ). mov a,r10 (j) transfers work area 1 (r 10 ) to s0 1 1 s1 accumulator. anl a,r1c (k) clears the accumulators low-order s0 0 0 0 three bits. (in this case, r 1c = 8h). jmp kl_calc to kl_calc. ; ;** ki data calculation ** ki_calc: mov a,r06 (l) transfers key scan counter (r 06 ) to ks3 ks2 ks1 ks0 accumulator. rl a rl a (m) shifts accumulator two bits leftward ks1 ks0 ks3 ks2 mov r09,a (n) stores accumulator values in a cc ? r 09 compare key data l (r 09 ). anl a,r02 (o) clears the high-order three bits of the 1 0 0 ks2 accumulator. (in this case, r 02 = 1h) orl a,r1b (p) sets the high-order two bits of 1 1 0 ks2 accumulator (in this case, r 1b = 0ch.) a cc ? r 09 mov r19,a (q) stores accumulator values in compare key data h (r 19 ). in a,p01 (r) transfers s 1 and s 0 data to s1 s0 1 1 accumulator. rl a rl a (s) shifts accumulator three bits leftward. 1 s1 s0 1 rl a ------------- ------------- ------------- ------------- ------------- -------------
151 chapter 6 program description clear bits 3, 2, and 0 of a a or compare key data h has the key on flag been set? key return check completed? kl_calc no_keys 1 compare key data h ? a clear low-order two bits of a krc_inc a ? key return check counter clear high-order two bits of a a or compare key data l clear status flag key scan completed eight times? shift key scan data one bit leftward increment key scan counter compare key data l ? a compare key data h ? 09h increment key return check counter set key on flag compare key data l ? a a ? compare key data l keys_out key_ret key_data (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (l) (m) (n) (p) (q) (s) (o) (k) (r) yes no no yes yes no single_k:
chapter 6 program description 152 accumulator values anl a,r0c (a) clears bits 3, 2, and 0 of accumulator 0 0 s0 0 (in this case, r 0c = 2h) orl a,r19 (b) performs or processing of 1 1 s0 ks2 accumulator values and compare key data h (r 19 ). mov r19,a (c) stores accumulator values in a cc ? r 19 compare key data h (r 19 ). mov a,r09 (d) transfers compare key data l (r 09 ) ks1 ks0 ks3 ks2 to accumulator. anl a,r1b (e) clears the low-order two bits of the ks1 ks0 0 0 accumulator. (in this case, r 1b =1100b) mov r09,a (f) stores accumulator values in a cc ? r 09 compare key data l (r 09 ). mov a,r0a (g) transfers key return check counter kr3 kr2 kr1 kr0 (r 0a ) to accumulator. anl a,r08 (h) clears the accumulators high-order 0 0 ks1 ks0 two bits. (in this case, r 0b =0011b). kl_calc: k i input crl a,r09 (i) performs or processing of ks1 ks0 kr1 kr0 accumulator values and compare s 1 input key data l (r 09 ). s0 ks2 ks1 ks0 mov r09,a (j) stores accumulator values to a cc ? r 09 compare key data l (r 09 ). ;** key combination check ** mov a,r16 scaf (k) determines whether or not the key on flag (r 16 ) has been set. jnc single_k if it has been cleared, processing branches to single_k. mov a,#09h mov r19,a single_k: mov a,r12 (m) sets the key on flag (r 16 ) (in this case, r 12 = 0fh). mov r16,a krc_inc: mov a,r0a inc a (n) increments the key return check counter (r 0a ). mov r0a,a jnc key_ret (o) determines whether or not the key return check has been completed four times (for k i input) or one time (for s 1 input). if it has not been completed the required number of times, processing branches to key_ret. no_key: stts #0101b (p) clears status flags. mov a,r06 inc a (q) increments key scan counter (r 06 ). mov r06,a jc key_data (r) determines whether or not the key scan has been completed eight times. mov a,r18 if it has been completed, processing branches to key_data. rl a mov r18,a mov a,r08 rl a (s) shifts the key scan data (r8) one bit leftward. mov r08,a jnc keys_out mov r8,#010h jmp keys_out (l) sets 9h to compare key data h (r 19 ). ------------- ------------- ------------- ------------- ------------- -------------
153 chapter 6 program description high-level output from k i/o (all pins) key data ? compare key data increment chattering counter confirmation key data ? key data has the key on flag been set? chattering count = first time has chattering occurred three times? confirmation key data = key data? is confirmation key data k29? key data = compare key data? key_data set k29 on flag is confirmation key data combination key data? clear k29 on flag clear continue flag data_set on_chat main to main processing continue flag 0h : do not continue 0fh: continue if k29 : k29 on flag = 0fh if not k29: k29 on flag = 0h (k) (l) (f) (e) (o) (j) (i) (n) (a) (b) (c) (d) (h) (g) yes no no yes yes no yes no yes no yes no yes no keycheck: k29check: kdat_set: data_set:
chapter 6 program description 154 ;*********************************************** ; transmit key data = on chattering key data?? ;*********************************************** key_data: out p0,#0ffh (a) sets all key scan output (via k i/o ) as high-level output. mov r8,#0f0h remark r8 is used for setting immediate data (r 16 : 0fh, r 08 : 0h). mov a,r16 scaf (b) determines whether or not the key on flag (r 16 ) jnc main has been set. if it has been cleared, processing branches to main. mov a,r00 xrl a,r0b (c) determines whether or not chattering scaf processing is occurring for the first time. jc keycheck (in this case, r 0b = #0011b.) if it is the first time, processing branches to keycheck. mov a,r14 xrl a,r18 remark in this case, r 16 = 0fh. xrl a,r19 scaf jnc main (d) determines whether or not the key data (r4) xrl a,r04 matches the compare key data (r9). xrl a,r09 (in this case, accumulator value = 0fh.) scaf if they do not match, processing branches to jnc main main. keycheck: mov a,r19 mov r14,a (e) stores compare key data (r9) in key data (r4). mov a,r09 mov r04,a mov a,r00 inc a (f) increments the chattering counter (r 00 ). mov r00,a scaf (g) determines whether or not chattering processing jnc on_chat has been completed three times. if it has not been completed three times, processing branches to on_chat. ;** key high check ** xrl a,r11 xrl a,r14 remark in this case, accumulator value = 0fh. scaf jnc kdat_set ;** key low check ** (h) determines whether or not the confirmation key xrl a,r01 data (r1) matches the key data (r4). xrl a,r04 (in this case, accumulator value = 0fh.) scaf if they do not match, processing branches to jc k29check kdat_set. if they match, processing branches to k29check. ksat_set: mov a,r14 mov r11,a (i) stores key data (r4) in confirmation key data mov a,r04 (r1). mov r01,a mov a,r08 (j) clears continue flag (r 03 ). (in this case, r 08 = mov r03,a 0h). --------------------------- --------------------------- --------------------------- --------------------------- --------------------------- --------------------------- --------------------------- ---------------------------
155 chapter 6 program description k29check: mov a,r0c remark in this case, r 0c = 2h. xrl a,r11 scaf jnc dbl_k_chk (k) determines whether or not k29 has been pressed. mov a,r01 (in this case, r 0b = 3h). xrl a,r0b if a key other than k29 has been pressed, scaf processing branches to k29_flg. jc k29_flg sbl_k_chk: mov a,#06h xrl a,r11 (l) determines whether or not the confirmation key scaf data is combination key data. jc data_set if it is combination key data, processing branches to data_set. mov a,r08 (m) sets 0h to the accumulator. (in this case, r 08 = 0h). k29_flg: mov r13,a (n) clears the k29 on flag (in this case, the accumulator value = 0h). (o) sets the k29 on flag (in this case, the accumulator value = 0fh). ------------------------------ ------------------------------
chapter 6 program description 156 custom code ? table data custom code ? table data data pointer ? confirmation key data table reference data code ? table data data_set trns to transmission processing (a) (b) (c) (d)
157 chapter 6 program description ;*********************************************** ; transmit data set ;*********************************************** data_set: ;** custom code ** mov r4,#custm1 (a) stores table data in custom code (r4). ;** custom code ** mov r5,#custm2 (b) stores table data in custom code (r5). ;** custom code ** mov a,r11 mov r10,a (c) sets confirmation key data (r1) in data pointer mov a,r01 (r0). mov r00,a mov r6,@r0 (d) stores table data in data code (r6). set_end: end ------------------------------
chapter 6 program description 158 6.3 transmission processing transmission processing transmits custom code, custom code, data code, and data code stored in the data memory, using the nec-r format that was described in chapter 2 transmission waveform . the transmission method uses a data table to store transmission times and sets the timer counter via a table reference operation. afterward, it enters halt mode (cancellation condition: timer) to enable transmission. a method such as that shown in figure 6-10 is used to ensure correct and simple time management. immediately after cancellation of halt mode, a similar method is used to set the transmission time data for the next transmission to the timer counter so that the transmission operation can be performed during a set time between halt modes. when carrier output is set to on (hereafter, this status is called h), the timer counters msb (output control bit) is set. when carrier output is set to off (hereafter, this status is called l), the timer counters msb (output control bit) is cleared. figure 6-9 shows the timer counters configuration. figure 6-9. configuration of timer counter figure 6-10. time management of timer counter the timers operation time can be calculated as [(setting + 1) x 8/fx]. when operating at 455 khz, mov t,#1ffh indicates that [(1ffh + 1) 8/(455 10 3 ) = 9.00 ms] has been set. . . t 9 t 8 t 7 t 6 t 5 t 4 output control bit t 3 t 2 t 1 t 0 9-bit count register timer counter halt (timer) set timer halt (timer) set timer halt #005h mov t, #1ffh ?sets 9.00-ms carrier output halt #005h ?halt mode until 9.00-ms has elapsed mov t, #07fh sets 2.25-ms carrier output as off any processing (as long as processing time is less than 9 ms)
159 chapter 6 program description 6.3.1 description of processing transmission processing includes the following seven types of processing. ? initialization ? leader code transmission ? code transmission (custom code, custom code, data code, and data code) ? stop bit transmission ? frame space transmission ? transmission of second and subsequent frames ? off chattering elimination processing each of these types of processing is described below. (1) initialization the initialization procedure for transmission processing is described in (a) and (b) below. (a) the key off check counter (r07) is set to 10 times (= 05h). (b) the data 1 transmit counter is set to 0dfh (for 24 bits). table 6-5 describes the counter contents. the data 1 transmit counter is used to count the number of times bit data 1 is transmitted within custom code or custom code that can affect the frame space transmission time. the number of data 1 occurrences in the data code and data code is fixed (at eight) and therefore does not affect the frame space transmission time. table 6-5. description of data 1 transmit counter (r9) counter value data 1 transmit counter description d0h number of data 1 occurrences: 0 to 7 to this status does not exist since the number of data 1 occurrences in data code e6h and data code is fixed (at eight). e7h number of data 1 occurrences: 8 number of data 1 occurrences in custom code and custom code: 0 e8h number of data 1 occurrences: 9 to 16 to number of data 1 occurrences in custom code and custom code: 1 to 8 efh f0h number of data 1 occurrences: 17 to 24 to number of data 1 occurrences in custom code and custom code: 9 to 16 f7h
chapter 6 program description 160 (2) leader code transmission the transmission method for the leader code is described in (a) to (f) below. (a) the table reference address (1a8h) for the leader code is set as follows. ? high-order address (0ah) is set to data pointer h (r10) ? low-order address (8h) of data 0 in bit data is set to data 0 (r08) (b) output data 0h for leader code is set to work area 2 (r1a). (c) a subroutine (bitout0f) is called to transmit the leader code as a one-bit transmission. (d) work area 2 (r1a) is shifted leftward and a bit judgment is performed. (e) the table reference address l for the judged bit is set to data pointer l to enable the transmission time to be set to the timer counter. (f) the leader code (h: 9.00 ms, l: 4.50 ms) is transmitted. (3) code transmission (custom code, custom code, data code, and data code) the code transmission method is described in (a) to (h) below. (a) the table reference addresses (1aah and 1ach) for bit data used for code transmission are set as follows. ? high-order address (0ah) is set to data pointer h (r10) ? low-order address (0ah) of data 0 in bit data is set to data 0 (r08) ? low-order address (0ch) of data 1 in bit data is set to data 1 (r18) (b) the following data is set to work area 2 (r1a) when each type of code is transmitted. ? custom code h (r14) ? custom code l (r04) ? custom code h (r15) ? custom code l (r05) ? data code h (r16) ? data code l (r06) ? data code h (r16 is fully inverted) ? data code l (r06 is fully inverted) (c) a subroutine is called to transmit the each type of code as a four-bit transmission. (d) work area 2 (r1a) is shifted leftward and a bit judgment is performed. if data 1 is judged, the number of data 1 occurrences is counted to enable frame space transmission. (e) the table reference address l for the judged bit is set to data pointer l to enable the transmission time to be set to the timer counter. (f) each type of code is transmitted. ? data 0 ... h: 0.56 ms, l: 0.56 ms ? data 1 ... h: 0.56 ms, l: 1.69 ms a key off check is performed during low level transmission of each bit. for a description of the key off check, see (7) off chattering elimination processing below. (g) steps (d) to (f) above are repeated until four bits have been transmitted. (h) steps (b) to (g) above are repeated until all transmissions from custom code h to data code l are completed.
161 chapter 6 program description (4) transmission of stop bit the method for transmitting stop bits is described in (a) to (f) below. (a) the table reference address (1aeh) for the stop bit is set as follows. ? high-order address (0ah) is set to data pointer h (r10) ? low-order address (0eh) of data 0 in bit data is set to data 0 (r08) (b) output data 0h for stop bit is set to work area 2 (r1a). (c) a subroutine is called to transmit the stop bit as a one-bit transmission. (d) work area 2 (r1a) is shifted leftward and a bit judgment is performed. (e) the table reference address l for the judged bit is set to data pointer l to enable the transmission time to be set to the timer counter. (f) the stop bit (h: 0.56 ms, l: 3.00 ms) is transmitted. (5) frame space transmission the code transmission time differs between transmission of the data 1 and data 0 bit data, with variation in the range of 59.06 ms to 77.06 ms. therefore, when transmitting code, the frame space transmission time varies according to the number of data 1 occurrences. however, since the number of data 1 occurrences is fixed (at eight) within the data code and data code, the frame space transmission times are not affected when these types of code are transmitted. the number of data 1 occurrences in the custom code and custom code do affect frame space transmission times. the number of data 1 occurrences are counted during transmission to enable responses to changes in transmission times. the frame space transmission times can be adjusted based on the count values. for details of data 1 counts, see (3) code transmission above. table 6-6 lists frame space times correspond to the number of data 1 occurrences. since the maximum value that can be set to the timer counter is 9.00 ms, the frame space is divided into the three patterns shown in figure 6-11 before being transmitted. differences between times shown in table 6-6 and figure 6-11 are margins of error during code transmission (such as when the data 0 low level time of 0.565 ms is set as 0.56 ms) which are absorbed by frame spaces.
chapter 6 program description 162 table 6-6. frame space times corresponding to the number of data 1 occurrences no. of data 1 transmission no. of data 1 transmission no. of data 1 transmission no. of data 1 transmission occurrences time (ms) occurrences time (ms) occurrences time (ms) occurrences time (ms) 8 48.940 13 43.315 18 37.690 23 32.065 9 47.815 14 42.190 19 36.565 24 30.940 10 46.690 15 41.065 20 35.440 11 45.565 16 39.940 21 34.315 12 44.440 17 38.815 22 33.190 remark since the number of data 1 occurrences in data code and data code is fixed (at eight), the data 1 values are never between 0 and 7. figure 6-11. method for dividing frame space transmission times (1/2) (a) when there are eight data 1 occurrences (data 1 transmission counter value: 0e7h) a: after transmitting the stop bit, the frame space is transmitted for 3.00 ms. b: a frame space is transmitted for the period corresponding to the number of data 1 occurrences (18.94 ms). c: if a key has been pressed and held, on chattering elimination processing (9.00 ms 3 times) is performed. in other cases, a frame space is transmitted for 27.00 ms. (b) when there are from 9 to 16 data 1 occurrences (data 1 transmission counter value range: 0e8h to 0efh) a: after transmitting the stop bit, the frame space is transmitted for 3.00 ms. b: a frame space is transmitted for the period corresponding to the number of data 1 occurrences (9.94 ms to 17.80 ms). c: if a key has been pressed and held, on chattering elimination processing (9.00 ms 3 times) is performed. in other cases, a frame space is transmitted for 27.00 ms. c b b 27.00 ms 0.94 ms 9.00 ms b a 9.00 ms 3.00 ms c b 27.00 ms 0.94 to 8.80 ms b a 9.00 ms 3.00 ms
163 chapter 6 program description figure 6-11. method for dividing frame space transmission times (2/2) (c) when there are from 17 to 24 data 1 occurrences (data 1 transmission counter value range: 0f0h to 0f7h) a: after transmitting the stop bit, the frame space is transmitted for 3.00 ms. b: a frame space is transmitted for the period corresponding to the number of data 1 occurrences (0.94 ms to 8.80 ms). c: if a key has been pressed and held, on chattering elimination processing (9.00 ms 3 times) is performed. in other cases, a frame space is transmitted for 27.00 ms. (6) transmission of second and subsequent frames until the current key is released or changed, code transmission of second and subsequent frames is repeated starting with the leader code in the same manner as for the first frame. this transmission method is described in (2) to (5) above. for a description of the key off check, see (7) off chattering elimination processing below. (7) off chattering elimination processing a key off check is performed during low level output of bit data. key off status is confirmed only when absence of key input (i.e., key off) has been judged for ten consecutive times during 34 times of low level output that includes the leader code and stop bit. if even one key input (key on) is detected during the ten consecutive times being checked, the ten-time counter is cleared and the count is restarted. if key off status is not confirmed during the entire 34-time check, the key is judged as being pressed and held. even if key off status is confirmed during transmission of one frame, initialization processing is not performed until at least two frames have been transmitted. figure 6-12. key off check during bit data transmission c b 27.00 ms 0.94 to 8.80 ms a 3.00 ms key off check (up to 34 times)
chapter 6 program description 164 6.3.2 detailed flow chart note as part of the main routine, the output data for the leader code is set to the accumulator (a) and the same data is set to work area 2 (r1a) via the called subroutine (bitout0c). set key off check counter for ten times initialize data 1 transmission counter data pointer h ? 0ah data 0 ? table data's address l work area 2 ? output data for leader code data 1, data 0 ? table data's address l trns bitout0f work area 2 ? custom code' h bitout0c work area 2 ? custom code' l work area 2 ? custom code h work area 2 ? custom code l bitout0c bitout0c bitout0c (b) (k) (l) (m) (o) (n) (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) note note note note note
165 chapter 6 program description ******** transmission processing ******** time9m equ 1ffh ; 9.00ms(9.002ms) ;########## p u b l i c ########## ; ;########## e x t e r n ########## extrn main ; main routine extrn key80 ; key check routine extrn fs_27ms ; frame space subroutine ;########## s t a r t ########## trns: mov r7,#0f5h (a) sets the key off check counter (r 07 ) for ten times ( = 5h). r 17 is used for immediate setting (r 17 = 0fh). mov r9,#0dfh (b) initializes (sets 0fh to) the data 1 transmission counter (r 09 ). ;*********************************************** ; leader code remark transmission of leader code (h: 9.00 ms, ;*********************************************** l: 4.50 ms) mov r0,#0a0h (c) sets the 0ah (high-order address of the table data for the bit data transmission time) to data pointer h (r 10 ). mov r8,#008h (d) sets the low-order address of the table data for the bit data transmission time to data 1 (r 18 ) and data 0 (r 08 ) (r 18 ? 0h, r 08 ? 8h). mov a,r18 (e) sets the output data (0h) for leader code to the accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0f (f) calls the bit output subroutine (for one-bit transmission: counter value = 0fh). ;*********************************************** ; custom code remark transmission of custom code ;*********************************************** (h: 0.56 ms, l: 0.56 or 1.69 ms) mov r8,#0cah (g) sets the low-order address of the table data for the custom code to data 1 (r 18 ) and data 0 (r 08 ) (r 18 ? ch, r 08 ? ah). mov a,r14 (h) sets output data h (r 14 ) for custom code to the accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (i) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). mov a,r04 (j) sets output data l (r 04 ) for custom code to the accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (k) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). ;*********************************************** ; custom code remark transmission of custom code ;*********************************************** (h: 0.56 ms, l: 0.56 or 1.69 ms) mov a,r15 (l) sets output data h (r 15 ) for custom code to the accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (m) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). mov a,r05 (n) sets output data l (r 05 ) for custom code to accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (o) calls the bit output subroutine (for four-bit transmission: counter value = 0ch).
chapter 6 program description 166 note as part of the main routine, the output data for the leader code is set to the accumulator (a) and the same data is set to work area 2 (r1a) by the called subroutine (bitout0c). work area 2 ? data code h 2 bitout0c work area 2 ? data code l bitout0c work area 2 ? data code h full inversion of work area 2 bitout0c work area 2 ? data code l full inversion of work area 2 bitout0c data 0 ? table data's address l work area 2 ? stop bit's output data bitout0f (c) (a) note (b) (g) (e) note (d) (c) note (h) note (i) (j) (f) (k) (l) note (m)
167 chapter 6 program description ;*********************************************** ; data code remark transmission of data code ;*********************************************** (h: 0.56 ms, l: 0.56 or 1.69 ms) mov a,r16 (a) sets output data h (r 16 ) for the data code to the accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (b) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). mov a,r06 (c) sets output data l (r 06 ) for the data code to the accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (d) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). ;*********************************************** ; data code remark transmission of data code ;*********************************************** (h: 0.56 ms, l: 0.56 or 1.69 ms) mov a,r16 (e) sets output data h (r 16 ) for the data code to the accumulator. xrl a,#0fh (f) the accumulators value is inverted to create output data for data code h. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (g) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). mov a,r06 (h) sets output data l (r 06 ) for the data code to the accumulator. xrl a,#0fh (i) the accumulators value is inverted to create output data for data code l. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0c (j) calls the bit output subroutine (for four-bit transmission: counter value = 0ch). ;*********************************************** ; stop bit remark transmits stop bit ;*********************************************** (h: 0.56 ms, l: 3 ms) mov r8,#00eh (k) sets the low-order address of table data having a stop bit carrier to data 0 (r 08 ). mov a,r18 (l) sets the output data (0h) for the stop bit to the accumulator. (the accumulators value is transferred to work area 2 as part of the bit output subroutine.) call bitout0f (m) calls the bit output subroutine (for one-bit transmission: counter value = 0fh).
chapter 6 program description 168 note if pressed continuously, continue flag = 0fh. key_on: set timer counter to 9 ms clear status flag set timer counter to 9 ms clear status flag clear msb of data 1 transmit counter l data pointer l ? data 1 transmit counter l is frame space at least 9 ms? is frame space at least 18 ms? timer counter ? table data clear status flag 3 set continue flag frame space = 27 ms frame space = 27 ms pressed continuously? key off? trns main key80 to main processing to key input processing halt mode (timer cancel) halt mode (timer cancel) halt mode (timer cancel) halt mode (timer cancel) (e) (n) (o) (a) (f) (k) (q) (b) (d) (c) (h) (g) (j) (i) (m) (s) (p) (r) (l) yes no yes no no yes yes no note t9_under:
169 chapter 6 program description ;*********************************************** ; frame space remark frame space transmission (l: 30.94 ms to ;*********************************************** 48.94 ms) mov a,r19 (a) judges the number of bit data 1 occurrences for scaf custom code (16 bits) as eight or less. jc t9_under if nine or above, processing branches to t9_under. halt #005h (b) halt mode: canceled when time counter reaches 00h. mov t,#time9m (c) if eight or less, sets timer counter to 9 ms (= 1ffh). stts #0101b (d) clears status flag. mov a,r09 (e) judges the number of bit data 1 occurrences for rl a custom code (16 bits) as zero or not zero. jc t9_under if 1 to 8, processing branches to t9_under. halt #005h (f) halt mode: canceled when time counter reaches 00h. mov t,#time9m (g) if zero, sets timer counter to 9 ms (= 1ffh) again for a total transmission time of 18 ms. t9_under: stts #0101b (h) clears status flag. mov a,r09 (i) clears the msb of the data 1 transmit counter l anl a,#0111b (r 09 ). mov r00,a (j) sets value of data 1 transmit counter l (r 09 ) to data pointer l (r 00 ). halt #005h (k) halt mode: canceled when time counter reaches 00h. mov t,@r0 (l) performs table reference to set a value from 0.940 ms to 8.815 ms to the timer counter according to the number of bit data 1 occurrences. stts #0101b (m) clears status flag. mov a,r03 (n) judges transmission of first frame (to check for scaf continue status). if transmitting the first frame, jnc key_on processing branches to key_on. mov a,r07 (o) if transmitting the second or subsequent frame scaf (continue status), it judges whether a key off jnc key80 status occurs during the transmission. if continue status is detected, processing branches to key80. ;** frame space = 27ms ** call fs_27ms (p) if a key off status is detected during bit data transmission, the remaining 27 ms of the frame space is output. halt #005h (q) halt mode: canceled when time counter reaches 00h. jmp main processing branches to initialization processing ; and main. key_on: mov a,r17 (r) sets continue flag (r 03 ) (in this case, mov r03,a r 17 = ofh). ;** frame space = 27ms ** call fs_27ms (s) calls subroutine for 27-ms output. jmp trns processing branches to trns. ; -------------------------------- -------------------------------- -------------------------------- -------------------------------- -------------------------------- --------------------------------
chapter 6 program description 170 shift work area 2 one bit leftward increment data 1 transmit counter h timer counter ? table data clear status flag increment data pointer l increment key off check counter clear status flag increment work counter timer counter ? table data increment data 1 transmit counter l bit data = 1? key off check completed 10 timers? work counter's count completed? halt mode (timer cancellation) halt mode (timer cancellation) bitout0f ret work area 2 ? output data work counter ? 0fh data pointer l ? data 1 initialize key off check counter bitout0c work area 2 ? output data work counter ? 0ch data pointer l ? data 0 overflow in data 1 transmit counter l? key input? ( a) ( b) ( e) ( c) ( d) (g) ( h) ( i) ( l) ( k) ( m) ( n) ( r) ( f) ( s) ( x) ( u) ( t) ( v) ( w) ( y) ( o) ( p) ( q) ( j) yes no yes no no yes no yes yes no bit_trans2: bit_trans1: bit_trns: bit_dat1: bitout:
171 chapter 6 program description ------------------------------ ------------------------------ ------------------------------ ------------------------------ ------------------------------ ------------------------------ ------------------------------ ------------------------------ ;************************************************* ;***** ***** ;***** transmit ***** ;***** subroutine : bit out ***** ;************************************************* bitoutof: mov r1a,a (a) sets output data to work area 2 (r 1a ). mov a,#0fh (b) sets 0fh to accumulator to set the transmit bit counter to count one time. jmp bitout processing branches to bitout. ; bitoutoc: mov r1a,a (c) sets output data to work area 2 (r 1a ). mov a,#0ch (d) sets 0ch to accumulator to set the transmit bit counter to count four times. bitout: mov r0a,a remark 0fh, 0eh, or 0ch can be set to the transmit bit counter (r 0a ). mov a,r1a rl a (e) shifts the output data one bit leftward. mov r1a,a jc bit_dat1 (f) judges whether bit data value is 0 or 1. if it is 1, processing branches to bit_dat1. ;** bit data = 0 ** mov a,r08 mov r00,a (g) sets data 0 (r 08 ) to data pointer l (r 00 ). jmp bit_trn processing branches to bit_trns. ; ;** bit data = 1 **; bit_dat1: mov a,r18 (h) sets data 1 (r 18 ) to data pointer l (r 00 ). mov r00,a mov a,r09 inc a (i) increments data 1 transmit counter l (r 09 ). mov r09,a jnc bit_trans (j) if there is no overflow in data 1 transmit counter l (r 09 ), processing branches to bit_trns. mov a,r19 inc a (k) increments data 1 transmit counter h (r 19 ). mov r19,a bit_trns: halt #005h (l) halt mode: canceled when time counter reaches 00h. mov t,@r0 (m) performs table reference to set transmit time data to timer counter. stts #0101b (n) clears status flag. mov a,r00 inc a (o) increments data pointer l (r 00 ). mov r00,a mov r00,a halt #005h (p) halt mode: canceled when time counter reaches 00h. mov t,@r0 (q) performs table reference to set transmit time data to timer counter. mov a,r07 inc a (r) judges whether key off status is maintained jc bit_trans2 during ten consecutive times. if key off status is confirmed, processing branches to bit_trans2. stts #1110b (s) determines whether or not key input exists. jnf bit_trans1 if a key has been pressed and held, processing branches to bit_trans1. ;** key input exists ** mov r7,#0f5h (t) initializes (= 5h) the key off check counter (r 07 ) if key input exists even once during the (10-time) key off check. jmp bit_trans2 processing branches to bit_trans2. ;
chapter 6 program description 172 ;** no key input ** bit_trans1: mov r07,a (u) increments key off check counter. bit_trans2: stts #0101b (v) clears status flag. mov a,r0a inc a jnc bitout (x) determines whether or not the transmit bit count has been completed. if not completed, processing branches to bitout. ret (y) end of processing ; end ------------------------------ (w) increments transmit bit counter (r 0a ).
173 chapter 6 program description set timer counter to 9 ms clear status flag set counter (a) to count three times. completed three times? frame space = 27 ms ret increment counter halt mode (timer cancellation) (g) (e) (d) (c) (a) (f) (b) yes no fs_27ms: fs_27ms0:
chapter 6 program description 174 ;************************************************* ;***** ***** ;***** frame space = 27ms ***** remark subroutine for outputting remaining 27 ;***** subroutine : fs 27ms ***** ms of frame space. ;***** ***** ;************************************************* fs_27ms: mov a,#0dh (a) sets counter (accumulator) to count three times (= 0dh). fs_27ms0: halt #005h (b) halt mode: canceled when time counter reaches 00h. mov t,#time9m (c) sets timer counter to 9 ms (= 1ffh). stts #0101b (d) clears status flag. inc a (e) increments counter (accumulator). jnc fs_27ms0 (f) determines whether or not three times have been counted. if they have not been counted, processing branches to fs_27ms0. ret (g) end of processing end
175 chapter 7 cautions on program revisions note the following caution points when modifying the key matrix or the number of keys. (1) when changing the number of keys from 80 to 64 ? delete the keys that are enclosed in broken lines in the following diagram (when doing so, if the s 1 /led pin is left unconnected, the number of keys can be changed without modifying the main program itself. note set by the program for internal pull-down resistor. (2) in addition to the modification described in (1) above, the s 1 /led pin can be used as an led pin: ? delete the keys that are enclosed in broken lines in the following diagram. ? change the s 1 /led pin so that b 2 (the bit that sets the i/o mode for the s 1 /led port) in the main programs control register 1 (p4) remains in output mode (bit value = 1). (in m pd6133 series products, setting the s 1 / led pin to output mode automatically eliminates internal pull-down resistance.) k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 note k i2 note k i1 note k i0 note k i/o6 k i/o7 s 0 note s 1 /led note rem v dd x out x in gnd reset pd6134 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 note k i2 note k i1 note k i0 note k i/o6 k i/o7 s 0 note s 1 /led note rem v dd x out x in gnd reset pd6134 m m
chapter 7 cautions on program revisions 176 note set by the program for internal pull-down resistor. k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 note k i2 note k i1 note k i0 note k i/o6 k i/o7 s 0 note s 1 /led note rem v dd x out x in gnd reset pd6134 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 note k i2 note k i1 note k i0 note k i/o6 k i/o7 s 0 note s 1 /led note rem v dd x out x in gnd reset pd6134 mm
chapter 8 cautions on use of this program the key combination specifications in this program provide only three valid key combination patterns: k29 + k30, k29 + k31, and k29 + k32. for this key matrix, if an ordinary key (k1 to k40) is pressed in combination with an expansion key (k41 to k80) on the same key source line, the expansion key will always be the valid key. for example, if k19 is pressed in combination with k59, then k59 is the valid key. 177
[memo] 178
chapter 9 program list as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 01-002 source = main80.asm e stno loc. 0bj. m i source statement 1 ;********************************************************************* 2 ;*** *** 3 ;*** multi-purpose remote control transmitter system *** 4 ;*** *** 5 ;*** cpu : upd6133 series *** 6 ;*** cpu clock : 455khz *** 7 ;*** trans. code: nec-r format (80key) *** 8 ;*** version : 2.0 *** 9 ;*** programmer : nec ic microcomputer systems corporation *** 10 ;*** *** 11 ;*** copyright(c) nec corporation 1995 *** 12 ;*** copyright(c) nims corporation 1995 *** 13 ;********************************************************************* 14 eject 179
chapter 9 program list 180 as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 01-003 source = main80.asm e stno loc. 0bj. m i source statement 15 001c time05m equ 01ch ;0.5ms (0.510ms) 16 01ff damytime equ 512-1 ;9.00ms (= 17.582us * 512) 17 18 ;########## p u b l i c ########## 19 public main 20 ; 21 ;########## e x t e r n ########## 22 ; 23 24 ;########## s t a r t ########## 25 26 ; control register (p3) reset:03h 27 ;===============================================================; 28 ; d9 d8 ! d7 ! d6 ! d5 ! d4 ! d3 ! d2 ! d1 ! d0 ! ; 29 ; ! ! d.p.! d.p.! d.p.! tctl! cary! mod1! mod0! ; 30 ; test mode! ! ad10! ad9 ! ad8 ! ad8 ! ! ! ! ; 31 ;---------------------------------------------------------------; 32 ; ! 0 ! * ! * ! 1/1 ! on ! fx,fx/8 ! 0 ; 33 ; set 0 !-----------------------------! ,fx/12(1/2) !----; 34 ; ! 0 ! * ! * ! 1/2 ! off ! ,fx/12(1/3) ! 1 ; 35 ;===============================================================; 36 37 ; control register (p4) reset:26h 38 ;===============================================================; 39 ; d9 d8 ! d7 ! d6 ! d5 ! d4 ! d3 ! d2 ! d1 ! d0 ! ; 40 ; ! ! ! ki!s0/s1! !s1/led! ki/0! s0 ! ; 41 ; ! ! ! pull! pull! ! mode ! mode! mode! ; 42 ;---------------------------------------------------------------; 43 ; ! 0 ! 0 ! off ! off ! 0 ! in ! in ! off ! 0 ; 44 ; x !------------------------------------------------!---; 45 ; ! 0 ! 0 ! on ! 0n ! 0 ! out ! out ! in ! 1 ; 46 ;===============================================================; 47 48 ;*********************************************** 49 ; control register initialize 50 ;*********************************************** 51 main: 52 0000 e6f8 efef out p0,#0ffh ;ki/0 all high 53 0002 e6fc e3e2 out p4,#032h 54 0004 e6fb e1e3 out p3,#013h ;set data pointer (p3:d8,d9) 55 0006 e6ff f7ff mov t,#damytime 56 0008 e3f1 e0e5 stts #0101b ;clear status flag 57 58 ;*********************************************** 59 ; ram initialize routine 60 ;*********************************************** 61 000a e6e1 e0e0 mov r1,#000h ;final key data (r1) = 00h 62 000c e6e3 e0e0 mov r3,#000h ;k29 on flag (r13),continuance falg (r03) = 00h 63 64 000e e2f1 e0e8 halt #008h ;stop mode (ki = high) 65 0010 e0e0 nop ;no operation command 66 0011 e6ff e0e7 mov t,#time05m ;set timer : 0.5ms 67 ; 68 end
181 chapter 9 program list as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 02-002 source = key80.asm e stno loc. 0bj. m i source statement 1 ;************************************************* 2 ;***** ***** 3 ;***** upd6133 series key check ***** 4 ;***** trans. code: nec-r format (80key) ***** 5 ;***** ***** 6 ;************************************************* 7 01ff time9m equ 1ffh ;9.00ms (9.002ms) 8 0050 custm1 equ 050h ;custom code = 0ah 9 00af custm1 equ 0afh ;custom code = f5h 10 11 ;########## p u b l i c ########## 12 public key80 13 ; 14 15 ;########## e x t e r n ########## 16 extrn main ;main routine 17 ; 18 19 ;########## s t a r t ########## 20 key80: 21 0013 e6e0 e0ec mov r0,#00ch ;chattering counter (r00) = 3 times 22 0015 e6ec e8e2 mov rc,#082h ;set immediate data : rc 23 ;************************************************* 24 ; on chattering 25 ;************************************************* 26 on_chat: 27 0017 e3f1 e0e5 stts #0101b ;clear status flag 28 0019 e6f8 efef out p0,#0ffh ;ki/0 all high 29 001b e6fc e3e3 out p4,#033h 30 001d e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 31 001f e6ff f7ff mov t,#time9m ;timer = 9.00ms 32 0021 e6e9 e0e0 mov r9,#000h ;comparative key data (r9) = 00h 33 0023 e6e6 e0e8 mov r6,#008h ;key flag (r16) = 00h, key scan counter (r06) = 08h 34 0025 e3f1 e0ee stts #1110b ;with input key (ki or s0 or s1) ? 35 0027 eff1 e0e0 jnf main ; else main: (without input key) 36 ; then (with input key) 37 0029 e6e8 e0e1 mov r8,#001h ;key scan data (r8) initialize : 001h 38 39 ;************************************************* 40 ; key scan 41 ;************************************************* 42 keys_out: 43 002b ffe8 mov a,r08 44 002c e5f8 out p00,a ;key scan data l (p00) output 45 oo2d fee8 mov a,r18 46 002e e4f8 out p10,a ;key scan data h (p10) output 47 ;+++++++++++++++++++++++++++++ 48 ;++ 100us wait ++ 49 ;+++++++++++++++++++++++++++++ 50 002f e6e2 efe1 mov r2,#0f1h ;set immediate data : r2 51 0031 e6eb ece3 miv rb,#0c3h ;set immediate data : rb 52 0033 e0e0 nop 53 0034 e0e0 nop 54 0035 e0e0 nop 55 0036 e0e0 nop
chapter 9 program list 182 as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 02-003 source = key80.asm e stno loc. 0bj. m i source statement 56 ;*********************************************** 57 ; key return check 58 ;*********************************************** 59 0037 e3f1 e0eb stts #1011b ;with input key (ki or s0 or s1) ? 60 0039 eff1 e9e8 jnf no_keys ; else no_keys: (without input key) 61 ; then (with input key) 62 003b e3f1 e0e3 stts #0011b ;with input ki (p11)? 63 003d eff1 e4e8 jnf s0s1calc ; else s0s1calc: (with input ki) 64 ; then (without input ki) 65 ;*******************************; then (ki(p11)without input) 66 ; ki data calculate 67 ;******************************* 68 003f fff9 in a,p01 69 0040 fcf3 rl a ;with input s1(p01)? 70 0041 ecf1 e0e0 jc main ; else main: (with input s1) 71 ; then (without input s1) 72 0043 feeb mov a,r1b ;r1b = 0ch 73 0044 e5ea mov r0a,a ;key return check counter (r0a) = 4 times (=0ch) 74 0045 fef9 in a,p11 75 0046 e8f1 e4ed jmp key_ret0 76 ; 77 78 ;******************************* 79 ; s0,s1 data calculate 80 ;******************************* 81 s0s1calc: 82 0048 e6e9 ebe0 mov r9,#0b0h 83 004a fee2 mov a,r12 ;r12 = 0fh 84 004b e5ea mov r0a,a ;set key return check counter (r0a) = 1 times (=0fh) 85 004c fff9 in a,p01 86 87 key_ret0: 88 004d e4e0 mov r10,a ;work (r10) = p11 or p01 89 004e e3f1 e0e5 stts #0101b ;clear status flag 90 key_ret: 91 0050 fee0 mov a,r10 92 0051 fef3 riz a 93 0052 e4e0 mov r10,a 94 0053 edf1 e9e3 jnc krc_inc ;with input key? 95 ;** with input key ** ; else krc_inc: (without input key) 96 0055 fee6 mov a,r16 ; then (with input key) 97 0056 faf3 scaf ;key flag (r16) = 0fh? 98 0057 edf1 e6e7 jnc key_calc ; else key_calc: (except for 0fh) 99 0059 fee3 mov a,r13 ; then (= 0fh) 100 005a faf3 scaf ;k29 on flag (r13) = 0fh? 101 005b edf1 e0e0 jnc main ; else main: (= except for 0fh) 102 ; then (= 0fh) 103 005d ffec mov a,roc ;roc = 02h 104 005e f4e9 xrl a,r19 105 005f faf3 scaf ;comparative key data = k29 (r19=odh) ? 106 0060 edf1 e0e0 jnc main ; then main: (key = except for k29) 107 0062 ffe9 mov a,r09 ; else (key = k29) 108 0063 f5eb xrl a,r0b ;r0b = 03h 109 0064 faf3 scaf ;comparative key data = k29 (r09=0ch) ? 110 0065 edf1 e0e0 jnc main ; then dbl_k_chk: (key = except for k29)
183 chapter 9 program list as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 02-004 source = key80.asm e stno loc. 0bj. m i source statement 111 112 ;******************************* 113 ; key data calculate 114 ;******************************* 115 key_calc: 116 0067 fff1 f4e0 mov a,#04h 117 0069 f4e9 xrl a,r19 118 006a faf3 scaf ;comparative key data h (r19) = 0bh ? 119 006b edf1 e7e5 jnc ki_calc ; else ki_calc: (ki data) 120 ;** s1 data calculation ** ; then (s1 data) 121 006d ffe6 mov a,r06 ;acc <-- key scan counter (r06) 122 006e fbf1 f7e0 anl a,#0111b 123 0070 e5e9 mov r09,a 124 0071 fee0 mov a,r10 ;acc <-- work 1 (r10) 125 0072 faec anl a,r1c ;r1c = 08h 126 0073 e8f1 e8e8 jmp kl_calc 127 ; 128 ;** ki data calculation ** 129 ki_calc: 130 0075 ffe6 mov a,r06 ;acc <-- key scan counter (r06) 131 0076 fcf3 rl a 132 0077 fcf3 rl a ;left shift (2 times) 133 0078 e5e9 mov r09,a ;comparative key data l (r09) <-- acc 134 0079 fbe2 anl a,r02 ;acc and 0001b (r02=01h) 135 007a fceb orl a,r1b ;acc or 1100b (r1b=0ch) 136 007b e4e9 mov r19,a ;comparative key data h (r19) <-- acc 137 007c fff9 in a,p01 ;acc <-- s1 and s0 data 138 007d fcf3 rl a ;left shift (3 times) 139 007e fcf3 rl a 140 007f fcf3 rl a 141 0080 fbec anl a,roc ;acc and 0010b (r0c=02h) 142 0081 fce9 orl a,r19 ;acc or comparative key data h (r19) 143 0082 e4e9 mov r19,a ;comparative key data h (r19) <-- acc 144 0083 ffe9 mov a,r09 ;acc <-- comparative key data l (r09) 145 0084 faeb anl a,r1b ;acc and 1100b (r1b=0ch) 146 0085 e5e9 mov r09,a ;comparative key data l (r09) <-- acc 147 0086 ffea mov a,r0a ;acc <-- key return check counter (r0a) 148 0087 fbeb anl a,r08 ;acc and 0011b (r08=03h) 149 kl_calc: 150 0088 fde9 orl a,r09 ;acc or comparative key data l (r09) 151 0089 e5e9 mov r09,a ;comparative key data l (r09) <-- acc 152 153 ;** double key check ** 154 008a fee6 mov a,r16 155 008b faf3 scaf ;key flag (r16) = 0fh? 156 008c edf1 e9e1 jnc single_k ; else single_k (single key) 157 008e fff1 f9e0 mov a,#09h ; then (double key) 158 0090 e4e9 mov r19,a 159 single_k: 160 0091 fee2 mov a,r12 ;r12 = 0fh 161 0092 e4e6 mov r16,a 162 163 krc_inc: 164 0093 ffea mov a,r0a 165 0094 f4f3 inc a ;key return check counter (r0a) increment
chapter 9 program list 184 as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 02-005 source = key80.asm e stno loc. 0bj. m i source statement 166 0095 e5ea mov r0a,a ;end of key return check ? 167 0096 edf1 e5e0 jnc key_ret ; else key_ret: (continuous) 168 ; then (end) 169 170 no_keys: 171 0098 e3f1 e0e5 stts #0101b ;clear status flag 172 009a ffe6 mov a,r06 173 009b f4f3 inc a ;key scan counter(r06) increment 174 009c e5e6 mov r06.a ;end of key scan number of 8 time ? 175 009d ecf1 eaeb jc key_data ; then key_data: (end) 176 009f fee8 mov a,r18 ; else (continuous) 177 00a0 fcf3 rl a ;key scan data h (r18) shift 178 00a1 e4e8 mov r18,a 179 00a2 ffe8 mov a,r08 180 00a3 fcf3 rl a 181 00a4 e5e8 mov r08,a ;key scan data l (r08) shift --> cy ? 182 00a5 edf1 e2eb jnc keys_out ; else keys_out: (key scan data a low rank) 183 00a7 e6e8 e1e0 mov r8,#010h ; then (key scan data a high rank) 184 00a9 e8f1 e2eb jmp keys_out 185 ; 186 187 ;*********************************************** 188 ; transmit key data = on chattering key data? 189 ;*********************************************** 190 key_data: 191 00ab e6f8 efef out p0,#0ffh ;ki/0 all high 192 00ad e6e8 efe0 mov r8,#0f0h ;set immediate data : r8 193 00af fee6 mov a,r16 194 00b0 faf3 scaf ;key flag (r16) = 0fh ? 195 00b1 edf1 e0e0 jnc main ; else main: (=except for 0fh) 196 00b3 ffe0 mov a,r00 ; then (= 0fh) 197 00b4 f5eb xrl a,r0b ;r0b = #0011b 198 00b5 faf3 scaf ;chattering counter (r00) = 1 times (=0dh)? 199 00b6 ecf1 ece3 jc keycheck ; then keycheck: (=0dh) 200 ; else (=0e-0fh) 201 00b8 fee4 mov a,r14 202 00b9 f4e8 xrl a,r18 ;r18 = 0fh 203 00ba f4e9 xrl a,r19 :acc = 0fh 204 00bb faf3 scaf ;key data h (r14) = comparative key data h (r19) 205 00bc edf1 e0e0 jnc main ; else main: (unmatch) 206 ; then (match) 207 00be f5e4 xrl a,r04 ;acc = 0fh 208 00bf f5e9 xrl a,r09 209 00c0 faf3 scaf ;key data l (r04) = comparative key data l (r09) 210 00c1 edf1 e0e0 jnc main ; else main: (unmatch) 211 keycheck: ; then (match) 212 00c3 fee9 mov a,r19 213 00c4 e4e4 mov r14,a ;key data h (r14) ? comparative key data h (r19) 214 00c5 ffe9 mov a,r09 215 00c6 e5e4 mov r04,a ;key data l (r04) ? comparative key data l (r09) 216 00c7 ffe0 mov a,r00 217 00c8 f4f3 inc a ;chattering counter (r00) increment 218 00c9 e5e0 mov r00,a 219 00ca faf3 scaf ;end of chattering routine of 3 time? 220 00cb edf1 e1e7 jnc on_chat ; else on_chat: (= 00h)
185 chapter 9 program list as6133 v1.01 << d6134 assemble list >> 01:00:00 08/29/96 page 02-006 source = key80.asm e stno loc. 0bj. m i source statement 221 ;** key high check ** ; then (= 0e-0fh) 222 00cd f4e1 xrl a,r11 ;acc = 0fh 223 00ce f4e4 xrl a,r14 224 00cf faf3 scaf ;final key data h (r11) = key data h (r14) ? 225 00d0 edf1 ede7 jnc kdat_set ; else kdat_set: (unmacth) 226 ;** key low check ** ; then (match) 227 00d2 f5e1 xrl a,r01 ;acc = 0fh 228 00d3 f5e4 xrl a,r04 229 00d4 faf3 scaf = ;final key data l (r01) = key data l (r04) ? 230 00d5 ecf1 eded jc k29check ; then k29check: (match) 231 kdat_set: ; else (unmacth) 232 00d7 fee4 mov a,r14 233 00d8 e4e1 mov r11,a ;final key data h (r11) <-- key data h (r14) 234 00d9 ffe4 mov a,r04 235 00da e5e1 mov r01,a ;final key data l (r01) <-- key data l (r04) 236 00db ffe8 mov a,r08 237 00dc e5e3 mov r03,a ;continuance flag = 00h (r08=00h) 238 239 k29check: 240 00dd ffec mov a,r0c ;r0c = 02h (k29=1dch) 241 00de f4e1 xrl a,r11 242 00df faf3 scaf ;final key data = k29 (r11=0bh)? 243 00e0 edf1 eee7 jnc dbl_k_chk ; then dbl_k_chk: (key = except for k29) 244 00e2 ffe1 mov a,r01 ; else (key = k29) 245 00e3 f5eb xrl a,r0b ;r0b = 03h 246 00e4 faf3 scaf ;final key data = k29 (r01=0ch)? 247 00e5 ecf1 eeee jc k29_flg ; then k29_flg: (key = except for k29) 248 ; else (key = k29) 249 dbl_k_chk: 250 00e7 fff1 f6e0 mov a,#06h 251 00e9 f4e1 xrl a,r11 252 00ea faf3 scaf ;final key data k29+ k30 or k31 or k32 (r11=09h) ? 253 00eb ecf1 eeef jc data_set ; then data_set: (key = except for double key) 254 00ed ffe8 mov a,r08 255 k29_flg: 256 00ee e4e3 mov r13,a ;k29 on flag = 00h (r08=00h) 257 ;*********************************************** 258 ; transmit data set 259 ;*********************************************** 260 data_set: 261 ;** custom code ** 262 00ef e6e4 e5e0 mov r4,#custm1 ;custom code(r4) <-- custom code 263 264 ;** custom code ** 265 00f1 e6e5 eaef mov r5,#custm2 ;custom code(r5) <-- custom code 266 267 ;** data code ** 268 00f3 fee1 mov a,r11 269 00f4 e4e0 mov r10,a ;data pointer h(r10) <-- final key data h(r11) 270 00f5 ffe1 mov a,r01 271 00f6 e5e0 mov r00,a ;data pointer l(r00) <-- final key data l(r01) 272 00f7 e7e6 mov r6,@r0 273 274 end
chapter 9 program list 186 as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 03-002 source = trans80.asm e stno loc. 0bj. m i source statement 1 ;************************************************* 2 ;***** ***** 3 ;***** upd6133 series transmit ***** 4 ;***** trans. code: nec-r format (80key) ***** 5 ;***** ***** 6 ;************************************************* 7 01ff time9m equ 1ffh ;9.00ms (9.002ms) 8 9 ;########## p u b l i c ########## 10 ; 11 12 ;########## e x t e r n ########## 13 extrn main ;main routine 14 extrn key80 ;key check routine 15 extrn fs_27ms ;frame space subroutine 16 ; 17 18 ;########## s t a r t ########## 19 trns: 20 00f8 e6e7 efe5 mov r7,#0f5h ;r17 : set immediate data (=0fh) 21 ;key off check counter (r07) = 10 times (=05h) 22 00fa e6e9 edef mov r9,#00fh ;data1 trans counter (r9) = dfh 23 ;************************************************* 24 ; leader code 25 ;************************************************* 26 00fc e6e0 eae0 mov r0,#0a0h ;data pointer h (r10) = 0ah 27 00fe e6e8 e0e8 mov r8,#008h ;set table address l 28 0100 fee8 mov a,r18 ;output data (work) <-- 00h (r18) 29 0101 e6f2 e8f1 e6f1 call bitoutof 30 31 ;************************************************* 32 ; custom code 33 ;************************************************* 34 0104 e6e8 ecea mov r8,#0cah ;set table address l 35 0106 fee4 mov a,r14 ;output data (work) <-- custom code h (r14) 36 0107 e6f2 e8f1 e6f6 call bitoutoc 37 38 010a ffe4 mov a,r04 ;output data (work) <-- custom code h (r04) 39 0108 e6f2 e8f1 e6f6 call bitoutoc 40 41 ;************************************************* 42 ; custom code 43 ;************************************************* 44 010e fee5 mov a,r15 ;output data (work) <-- custom code h (r15) 45 010f e6f2 e8f1 e6f6 call bitoutoc 46 47 0112 ffe5 mov a,r05 ;output data (work) <-- custom code l (r05) 48 0113 e6f2 e8f1 e6f6 call bitoutoc 49 50 ;************************************************* 51 ; custom code 52 ;************************************************* 53 0116 fee6 mov a,r16 ;utput data (work) <-- data code h (r16) 54 0117 e6f2 e8f1 e6f6 call bitoutoc 55
187 chapter 9 program list as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 03-003 source = trans80.asm e stno loc. 0bj. m i source statement 56 011a ffe6 mov a,r06 ;output data (work) <-- data code l (r06) 57 011b e6f2 e8f1 e6f6 call bitoutoc 58 59 ;*********************************************** 60 ; data coce 61 ;*********************************************** 62 011e fee6 mov a,r16 ;output data (work) <-- data code h (r16) 63 011f f4e7 xrl a,r17 ;r17 = 0fh 64 0120 e6f2 e8f1 e6f6 call bitoutoc 65 66 0123 ffe6 mov a,r06 ;output data (work) <-- data code l (r06) 67 0124 f4e7 xrl a,r17 ;r17 = 0fh 68 0125 e6f2 e8f1 e6f6 call bitoutoc 69 70 ;*********************************************** 71 ; stop bit 72 ;*********************************************** 73 0128 e6e6 e0ee mov r8,#00eh ;set table address l 74 012a fee8 mov a,r18 ;output data (work) <-- 00h (r18) 75 012b e6f2 e8f1 e6f1 call bitoutof 76 77 ;*********************************************** 78 ; frame space 79 ;*********************************************** 80 012e fee9 mov a,r19 81 012f faf3 scaf ;frame space > 9.00ms ? 82 0130 ecf1 e4f0 jc t9_under ; then t9_under: (more than 9.00ms) 83 ; else (less than 9.00ms) 84 0132 e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 85 0134 e6ff f7ff mov t,#time9m 86 0136 e3f1 e0e5 stts #0101b ;clear status flag 87 88 0138 ffe9 mov a,r09 89 0139 fcf3 rl a ;frame space > 18.00ms ? 90 013a ecf1 e4f0 jc t9_under ; then t9_under: (less than 18.00ms) 91 ; else (more than 18.00ms) 92 013c e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 93 013e e6ff f7ff mov t,#time9m 94 95 t9_under: 96 0140 e3f1 e0e5 stts #0101b ;clear status flag 97 0142 ffe9 mov a,r09 98 0143 fbf1 f7e0 anl a,#0111b 99 0145 e5e0 mov r00,a 100 0146 e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 101 0148 e7ff mov t,@r0 102 0149 e3f1 e0e5 stts #0101b ;clear status flag 103 104 014b ffe3 mov a,r03 105 014c faf3 scaf ;continuously pressed key ? 106 014d edf1 e5fa jnc key_on ; else key_on: (1st. frame) 107 014f ffe7 mov a,r07 ; then (since 2nd. frame) 108 0150 faf3 scaf ;without input key ? 109 0151 edf1 e1e3 jnc key80 ; then key80: (with input key) 110 ;** frame space = 27ms ** ; else (without input key)
chapter 9 program list 188 as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 03-004 source = trans80.asm e stno loc. 0bj. m i source statement 111 0153 extrn call fs_27ms 112 0156 e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 113 0158 e8f1 e0e0 jmp main 114 ; 115 key_on: 116 015a fee7 mov a,r17 117 015b e5e3 mov r03,a ;continuance flag (r03) = 0fh (r17=0fh) 118 ;** frame space = 27ms ** 119 015c extrn call fs_27ms 120 015f e8f1 efe8 jmp trns 121 ; 122 123 ;************************************************* 124 ;***** ***** 125 ;***** transmit ***** 126 ;***** subroutine : bit out ***** 127 ;***** ***** 128 ;************************************************* 129 bitoutof: 130 0161 e4ea mov r1a,a ;set output data (1 bit output) 131 0162 fff1 ffe0 mov a,#0fh ;send bit counter = 1 times (=0fh) 132 0164 e8f1 e6f9 jmp bitout 133 ; 134 bitoutoc: 135 0166 e4ea mov r1a,a ;set output data (4 bit output) 136 0167 fff1 fce0 mov a,#0ch ;send bit counter = 4 times (=0ch) 137 138 bitout: 139 0169 e5ea mov r0a,a ;send bit counter (r0a) = 0ch or 0eh or 0fh 140 141 016a feea mov a,r1a 142 016b fcf3 rl a 143 016c e4ea mov r1a,a ;bit data = 1 ? 144 016d ecf1 e7f3 jc bit_dat1 ; then bit_dat1: (bit data = 1) 145 ;** bit data = 0 ** ; else (bit data = 0) 146 016f ffe8 mov a,r08 ;set data pointer l (r00) <-- data0 (r08) 147 0170 e5e0 mov r00,a 148 0171 e8f1 e7fd jmp bit_trns 149 ; 150 ;** bit data = 1 **; 151 bit_dat1: 152 0173 fee8 mov a,r18 ;set data pointer l(r00) <-- data1 (r18) 153 0174 e5e0 mov r00,a 154 0175 ffe9 mov a,r09 155 0176 f4f3 inc a ;data 1 transmit counter l (r09) increment 156 0177 e5e9 mov r09,a ;data 1 transmit counter l (r09) = overflow ? 157 0178 edf1 e7fd jnc bit_trns ; else bit_trns: (data 1 transmit counter l <= 0fh) 158 017a fee9 mov a,r19 ; then (data 1 transmit counter l > 0fh) 159 017b f4f3 inc a ;data 1 transmit counter h(r19) increment 160 017c e4e9 mov r19,a 161 bit_trns: 162 017d e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 163 017f e7ff mov t,@r0 164 0180 e3f1 e0e5 stts #0101b ;clear status flag 165 0182 ffe0 mov a,r00
189 chapter 9 program list as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 03-005 source = trans80.asm e stno loc. 0bj. m i source statement 166 0183 f4f3 inc a ;data pointer l (r00) increment 167 0184 e5e0 mov r00,a 168 0185 e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 169 0187 e7ff mov t,@r0 170 171 0188 ffe7 mov a,r07 172 0189 f4f3 inc a ;key off check counter (r07) increment 173 018a ecf1 e9f5 jc bit_trans2 ;key off check counter (r07) = end of 10 times ? 174 ; then bit_trans2: (end of 10 times) 175 ; else (less than 10 times) 176 018c e3f1 e0ee stts #1110b ;with input key ? 177 018e eff1 e9f4 jnf bit_trans1 ; else bit_trans1: (with input) 178 ;** with input key ** ; then (without input) 179 0190 e6e7 efe5 mov r7, #0f5h ;key off check counter (r07) = 05h 180 0192 e8f1 e9f5 jmp bit_trans2 181 ; 182 ;** without input key ** 183 bit_trans1: 184 0194 e5e7 mov r07,a 185 186 bit_trans2: 187 0195 e3f1 e0e5 stts #0101b ;clear status falg 188 0197 ffea mov a,r0a 189 0198 f4f3 inc a ;send bit counter (r0a) increment 190 0199 edf1 e6f9 jnc bitout 191 019b e8f2 ret 192 ; 193 end total errors = 0 total warnings = 0 end of list
chapter 9 program list 190 as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 04-002 source = dtable80.tbl e stno loc. 0bj. m i source statement 1 ;************************************************* 2 ;***** ***** 3 ;***** upd6133 series data table ***** 4 ;***** trans. code: nec-r format (80key) ***** 5 ;***** ***** 6 ;************************************************* 7 01ff time9m equ 1ffh ;9.00ms (9.002ms) 8 9 ;########## p u b l i c ########## 10 public datacode 11 public fs_27ms 12 ; 13 14 datacode: 15 ;************************************** 16 ;***** data code ***** 17 ;***** double key ***** 18 ;************************************** 19 019d org 19dh 20 ;** k29 + k30 ** 21 019d e0e9 dw 009h ;k29 + k30 : key data = 70h 22 ;** k29 + k31 ** 23 019e e8e9 dw 089h ;k29 + k31 : key data = 71h 24 ;** k29 + k32 ** 25 019f e4e9 dw 049h ;k29 + k32 : key data = 72h 26 ; 27 28 ;************************************** 29 ;***** frame space ***** 30 ;***** time data ***** 31 ;org 1a0h ***************************** 32 01a0 e7ed dt 1f4h ;counter:000 = 8.815ms (8.809ms) 33 01a1 e6ed dt 1b4h ;counter:001 = 7.690ms (7.683ms) 34 01a2 e5ed dt 174h ;counter:010 = 6.565ms (6.558ms) 35 01a3 e4ed dt 134h ;counter:011 = 5.440ms (5.433ms) 36 01a4 e3ed dt 0f4h ;counter:100 = 4.315ms (4.308ms) 37 01a5 e2ed dt 0b4h ;counter:101 = 3.190ms (3.182ms) 38 01a6 e1ed dt 074h ;counter:110 = 2.065ms (2.057ms) 39 01a7 e0ed dt 034h ;counter:111 = 0.940ms (0.932ms) 40 ; 41 42 ;************************************** 43 ;***** time data ***** 44 ;org 1a8h ***************************** 45 ;** leader code ** 46 01a8 ffff dt 3ffh ;carrier on : 9.000ms (9.002ms) 47 01a9 f3ff dt 0ffh ;carrier off : 4.500ms (4.501ms) 48 ;** bit data 0 ** 49 01aa f8f7 dt 21fh ;carrier on : 0.560ms (0.563ms) 50 01ab f0f7 dt 01fh ;carrier off : 0.565ms (0.563ms) 51 ;** bit data 1 ** 52 01ac f8f7 dt 21fh ;carrier on : 0.560ms (0.563ms) 53 01ad f1f7 dt 05fh ;carrier off : 1.690ms (1.687ms) 54 ;** stop bit ** 55 01ae f8f7 dt 21fh ;carrier on : 0.560ms (0.563ms)
191 chapter 9 program list as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 04-003 source = dtable80.tbl e stno loc. 0bj. m i source statement 56 01af e2fa dt 0a9h ;carrier off : 3.00ms (2.989ms) 57 ; 58 59 ;************************************** 60 ;***** data code ***** 61 ;***** single key ***** 62 ;************************************** 63 01b0 org 1b0h 64 ;** k33 - k40 ** 65 01b0 e0e4 dw 004h ;k33 : data code = 20h 66 01b1 e8e4 dw 084h ;k34 : data code = 21h 67 01b2 e4e4 dw 044h ;k35 : data code = 22h 68 01b3 ece4 dw 0c4h ;k36 : data code = 23h 69 01b4 e2e4 dw 024h ;k37 : data code = 24h 70 01b5 eae4 dw 0a4h ;k38 : data code = 25h 71 01b6 e6e4 dw 064h ;k39 : data code = 26h 72 01b7 eee4 dw 0e4h ;k40 : data code = 27h 73 ; 74 ;** k73 + k80 ** 75 01b8 e1e2 dw 012h ;k73 : data code = 48h 76 01b9 e9e2 dw 092h ;k74 : data code = 49h 77 01ba e5e2 dw 052h ;k75 : data code = 4ah 78 01bb ede2 dw 0d2h ;k76 : data code = 4bh 79 01bc e3e2 dw 032h ;k77 : data code = 4ch 80 01bd ebe2 dw 0b2h ;k78 : data code = 4dh 81 01be e7e2 dw 072h ;k79 : data code = 4eh 82 01bf efe2 dw 0f2h ;k80 : data code = 4fh 83 ; 84 85 01c0 org 1c0h 86 ;** k1 - k16 ** 87 01c0 e0e0 dw 000h ;k 1 : data code = 00h 88 01c1 e8e0 dw 080h ;k 2 : data code = 01h 89 01c2 e4e0 dw 040h ;k 3 : data code = 02h 90 01c3 ece0 dw 0c0h ;k 4 : data code = 03h 91 01c4 e2e0 dw 020h ;k 5 : data code = 04h 92 01c5 eae0 dw 0a0h ;k 6 : data code = 05h 93 01c6 e6e0 dw 060h ;k 7 : data code = 06h 94 01c7 eee0 dw 0e0h ;k 8 : data code = 07h 95 01c8 e1e0 dw 010h ;k 9 : data code = 08h 96 01c9 e9e0 dw 090h ;k10 : data code = 09h 97 01ca e5e0 dw 050h ;k11 : data code = 0ah 98 01cb ede0 dw 0d0h ;k12 : data code = 0bh 99 01cc e3e0 dw 030h ;k13 : data code = 0ch 100 01cd ebe0 dw 0b0h ;k14 : data code = 0dh 101 01ce e7e0 dw 070h ;k15 : data code = 0eh 102 01cf efe0 dw 0f0h ;k16 : data code = 0fh 103 ; 104 ;** k17 - k32 ** 105 01d0 e0e8 dw 008h ;k17 : data code = 10h 106 01d1 e8e8 dw 088h ;k18 : data code = 11h 107 01d2 e4e8 dw 048h ;k19 : data code = 12h 108 01d3 ece8 dw 0c8h ;k20 : data code = 13h 109 01d4 e2e8 dw 028h ;k21 : data code = 14h 110 01d5 eae8 dw 0a8h ;k22 : data code = 15h
chapter 9 program list 192 as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 04-004 source = dtable80.tbl e stno loc. 0bj. m i source statement 111 01d6 e6e8 dw 068h ;k23 : data code = 16h 112 01d7 eee8 dw 0e8h ;k24 : data code = 17h 113 01d8 e1e8 dw 018h ;k25 : data code = 18h 114 01d9 e9e8 dw 098h ;k26 : data code = 19h 115 01da e5e8 dw 058h ;k27 : data code = 1ah 116 01db ede8 dw 0d8h ;k28 : data code = 1bh 117 01dc e3e8 dw 038h ;k29 : data code = 1ch 118 01dd ebe8 dw 0b8h ;k30 : data code = 1dh 119 01de e7e8 dw 078h ;k31 : data code = 1eh 120 01df efe8 dw 0f8h ;k32 : data code = 1fh 121 ; 122 ;** k41 - k56 ** 123 01e0 e1e4 dw 014h ;k41 : data code = 28h 124 01e1 e9e4 dw 094h ;k42 : data code = 29h 125 01e2 e5e4 dw 054h ;k43 : data code = 2ah 126 01e3 ede4 dw 0d4h ;k44 : data code = 2bh 127 01e4 e3e4 dw 034h ;k45 : data code = 2ch 128 01e5 ebe4 dw 0b4h ;k46 : data code = 2dh 129 01e6 e7e4 dw 074h ;k47 : data code = 2eh 130 01e7 efe4 dw 0f4h ;k48 : data code = 2fh 131 01e8 e0ec dw 00ch ;k49 : data code = 30h 132 01e9 e8ec dw 08ch ;k50 : data code = 31h 133 01ea e4ec dw 04ch ;k51 : data code = 32h 134 01eb ecec dw 0cch ;k52 : data code = 33h 135 01ec e2ec dw 02ch ;k53 : data code = 34h 136 01ed eaec dw 0ach ;k54 : data code = 35h 137 01ee e6ec dw 06ch ;k55 : data code = 36h 138 01ef eeec dw 0ech ;k56 : data code = 37h 139 ; 140 ;** k57 - k72 ** 141 01f0 e1ec dw 01ch ;k57 : data code = 38h 142 01f1 e9ec dw 09ch ;k58 : data code = 39h 143 01f2 e5ec dw 05ch ;k59 : data code = 3ah 144 01f3 edec dw 0dch ;k60 : data code = 3bh 145 01f4 e3ec dw 03ch ;k61 : data code = 3ch 146 01f5 ebec dw 0bch ;k62 : data code = 3dh 147 01f6 e7ec dw 07ch ;k63 : data code = 3eh 148 01f7 efec dw 0fch ;k64 : data code = 3fh 149 01f8 e0e2 dw 002h ;k65 : data code = 40h 150 01f9 e8e2 dw 082h ;k66 : data code = 41h 151 01fa e4e2 dw 042h ;k67 : data code = 42h 152 01fb ece2 dw 0c2h ;k68 : data code = 43h 153 01fc e2e2 dw 022h ;k69 : data code = 44h 154 01fd eae2 dw 0a2h ;k70 : data code = 45h 155 01fe e6e2 dw 062h ;k71 : data code = 46h 156 01ff eee2 dw 0e2h ;k72 : data code = 47h 157 ; 158 159 160 161 ;************************************************* 162 ;***** ***** 163 ;***** frame space = 27ms ***** 164 ;***** subroutine : fs 27ms ***** 165 ;***** *****
193 chapter 9 program list as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 04-005 source = dtable80.tbl e stno loc. 0bj. m i source statement 166 ;************************************************* 167 fs_27ms: 168 0200 fff1 fde0 mov a,#00h ;counter(acc) = 3 times (=0dh) 169 fs_27ms0: 170 0202 e2f1 e0e5 halt #005h ;halt mode (timer = 00h) 171 0204 e6ff f7ff mov t,#time9m ;timer = 9.00ms 172 0206 e3f1 e0e5 stts #0101b ;status flag clear 173 0208 f4f3 inc a ;more than 27ms ? 174 0209 edf1 f0e2 jnc fs_27ms0 ; else fs_27ms0: (frame space < 27ms) 175 020b e8f2 ret ; then ret (frame space = 27ms) 176 ; 177 end total errors = 0 total warnings = 0 end of list
chapter 9 program list 194 as6133 v1.01 << d6134 assemble list >> 01:00:01 08/29/96 page 05-002 source = option.asm e stno loc. 0bj. m i source statement 1 ;************************************** 2 ;***** set option ***** 3 ;************************************** 4 option 5 0000 0001 usepoc 6 endop 7 end total errors = 0 total warnings = 0 end of list
although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6465-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec corporation semiconductor solution engineering division technical information support dept. fax: 044-548-7900 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 97.8 name company from: tel. fax facsimile message

▲Up To Search▲

Price & Availability of UPD6132MC-XXX-5A4-E2

	To Download UPD6132MC-XXX-5A4-E2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .